Hardware Timestamping on Packet-Oriented Bus
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Solution Overview
Problem
Existing timestamping systems on packet-oriented buses, such as PCIe, suffer from reduced accuracy due to latency and timing variability caused by software-based methods, which are dependent on the microprocessor's load and not directly connected to the event source.
Innovation Solution
Implementing digital logic directly on the packet-oriented bus to detect data packet formats, determine timestamps, and generate reports addressed to connected devices, thereby reducing latency and increasing accuracy by being closer to the event source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software-based timestamping is used on the microprocessor, then the system can determine event times, but the timestamp accuracy is reduced due to latency and microprocessor load variability
Solution Approach 1:
The patent introduces digital logic circuitry as an intermediary component between the PCIe bus and the microprocessor. This intermediary performs timestamp generation in hardware, capturing event times directly from the bus without requiring microprocessor intervention, thereby eliminating the latency and accuracy issues associated with software-based timestamping.
Solution Approach 2:
The patent replaces the software-based timestamping mechanism (which runs on the microprocessor) with a hardware-based digital logic system. This substitution moves the timestamping function from the software/executive layer to the hardware/circuit layer, providing deterministic timing independent of microprocessor load.
2Reliability
If software-based timestamping is used on the microprocessor, then the system can record event times, but the timestamping is dependent on microprocessor load causing timing variability
Solution Approach 1:
The digital logic circuitry acts as an intermediary that handles timestamp generation independently of the microprocessor. This mediator captures event times directly from the PCIe bus and stores them in timestamp registers, making the timestamping process reliable and consistent regardless of microprocessor activity or load conditions.
Solution Approach 2:
The timestamping system becomes self-service by using dedicated hardware resources (digital logic, timestamp registers, and PCIe bus access) that operate autonomously without requiring microprocessor execution. The system serves its own timestamping needs through hardware mechanisms rather than relying on the microprocessor's software routines.
3Measurement precision
If digital logic is implemented directly on the packet-oriented bus, then timestamp accuracy is enhanced and latency is reduced, but the device complexity increases
Solution Approach 1:
The patent segments the timestamping function from the main microprocessor system and implements it as a separate, dedicated digital logic module on the PCIe bus. This segmentation isolates the complex hardware timestamping logic from the general-purpose microprocessor, providing high-precision timestamping while keeping the overall system architecture manageable through functional separation.
Data Source
AI summary
An example method is performed on a packet-oriented bus at a point between a source of a data packet and a destination of a data packet. The example method includes detecting a format of the data packet on the packet-oriented bus; determining a time at which the data packet was detected; generating a timestamp report containing the time, with the timestamp report being addressed to a device connected to the packet-oriented bus; and outputting the timestamp report to the device. Detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus.