Hardware Trie Lookup Without Sequential Logic for Packet Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently managing packet traffic and data structures, particularly in handling hash functions and logging packet and byte count information, as existing architectures require sequential logic elements and are not scalable for increased throughput.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a transactional memory with a hardware trie structure and dedicated hardware circuits, including a state machine array and pipeline, to perform atomic operations and lookups without sequential logic, enabling efficient packet processing and data management across a configurable mesh Command/Push/Pull data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential logic elements are used in the memory structure, then the memory can be accessed, but the processing throughput is limited and scalability is reduced
Solution Approach 1:
The patent extracts sequential logic elements from the memory structure entirely, replacing them with a pure combinatorial logic hardware trie. This removal eliminates the throughput bottleneck while maintaining memory access functionality through a different architectural approach based on content-addressable lookup tables.
Solution Approach 2:
The patent substitutes the mechanical sequential logic system with a combinatorial logic system. Instead of using sequential circuits with state elements that process data step-by-step, the invention uses combinatorial logic circuits that perform parallel content-addressable lookup operations, dramatically increasing processing throughput.
2Productivity
If multiple microengines are added to increase processing power, then more packet processing can be performed, but memory contention increases and efficiency decreases
Solution Approach 1:
The patent segments the memory access function into multiple independent hardware tries, each capable of handling lookup operations autonomously. This segmentation allows multiple microengines to access different trie structures simultaneously without contending for the same memory resources, eliminating the scalability bottleneck.
Solution Approach 2:
The hardware trie structure serves multiple functions simultaneously: it acts as both the memory storage structure and the lookup processing engine. This multi-functionality eliminates the need for separate memory access control logic, allowing multiple microengines to perform memory operations concurrently without traditional memory contention.
3Speed
If a hardware trie structure with no sequential logic is implemented, then processing speed increases, but the device complexity in terms of combinatorial logic increases
Solution Approach 1:
The patent transitions from one-dimensional sequential processing to multi-dimensional parallel processing by organizing data in a trie structure with multiple levels and branches. This dimensional change allows the combinatorial logic to evaluate multiple data paths simultaneously, achieving high speed despite increased structural complexity.
Data Source
AI summary
A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.