Hardware Trie Lookup Without Sequential Logic for Recursive Search
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements due to limitations in processing power and memory access, particularly in identifying data structures using hash functions and logging packet and byte count information.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable mesh Command/Push/Pull data bus, enabling Atomic Look-up Add and Lock (ALAL) and Stats Add-and-Update (AU) commands to efficiently manage hash tables and packet counts, and a hardware trie structure for lookup operations, utilizing dedicated hardware circuits to optimize processing without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple microengines access the same memory resources via a common bus, then processing power is increased, but memory contention and access efficiency deteriorate
Solution Approach 1:
The memory system is segmented into multiple independent memory banks (first memory bank, second memory bank, third memory bank) that can be accessed simultaneously by different microengines. Each memory bank has dedicated access paths, eliminating the single bus bottleneck and allowing parallel memory operations across multiple processing units.
2Productivity
If hash table operations are performed using conventional memory access, then data structure identification is achieved, but processing speed and throughput are limited
Solution Approach 1:
The system pre-positions multiple memory banks with different data structures (hash tables, trie structures) before processing begins. Microengines can immediately perform hash table operations and lookups without waiting for sequential memory access, as the required data structures are already loaded and accessible in parallel from multiple banks.
Solution Approach 2:
The patent transitions from single-dimension sequential memory access to multi-dimensional parallel access by organizing memory resources into multiple banks that can be simultaneously accessed. This dimensional expansion allows multiple microengines to perform hash operations and data structure identification in parallel, dramatically increasing throughput.
3Productivity
If conventional memory structures are used for packet count logging, then information storage is achieved, but processing efficiency and atomic operation capability deteriorate
Solution Approach 1:
The memory banks are designed to autonomously handle atomic operations for packet and byte count logging. When a microengine writes to a memory location, the system automatically performs lock-check-write sequences without requiring processor intervention, ensuring atomicity and preventing race conditions while maintaining high processing efficiency.
Data Source
AI summary
A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.