Hardware Trojan Detection in IC Netlists via Macro Comparison

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Solution Overview

Problem

Existing methods are inefficient and ineffective in detecting and masking hardware Trojans in complex integrated circuits, leading to security concerns, circuit failures, and sensitive information leakage, due to their inability to handle complex logic patterns and exponential time complexity.

Innovation Solution

A method that compares netlists to detect and locate hardware Trojans by extracting arithmetic macros, using reverse engineering and formal verification techniques to apply patches and restore the circuit to its original specification, reducing runtime complexity and ensuring 100% detection of Trojans.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional detection methods are used to identify hardware Trojans in complex IC designs, then the detection process can be performed, but the detection efficiency is low and time complexity is exponential

Engineering Contradiction:
Improvedetection efficiencyVSAvoiddetection time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the complex IC design into multiple netlists representing different design versions or iterations. By comparing these segmented netlists, the system can efficiently identify hardware Trojans without needing to analyze the entire complex circuit from scratch, thereby improving detection efficiency and reducing time complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by generating multiple netlists during the design process before final verification. These pre-prepared netlists can be quickly compared to detect Trojans, avoiding the need for time-consuming analysis during the verification stage and thus reducing overall detection time.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If existing detection methods are applied to complex logic patterns, then some Trojans can be detected, but the detection effectiveness is insufficient and resource consumption is high

Engineering Contradiction:
Improvedetection effectivenessVSAvoidresource consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent creates copies of the circuit design in the form of multiple netlists that represent different design versions. By comparing these copies rather than analyzing the original complex circuit repeatedly, the system achieves high detection effectiveness with reduced resource consumption, as the comparison operation is computationally less intensive than full circuit analysis.

Inventive Principle:
Principle #26Copying

3Measurement precision

If manual inspection methods are used to verify circuit security, then detailed analysis can be performed, but the process is too slow for modern complex circuits

Engineering Contradiction:
Improveanalysis precisionVSAvoidverification speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent introduces an intermediary automated comparison system that operates between manual inspection and the final verification result. This intermediary system performs automated netlist comparisons with high precision, maintaining the analytical rigor of manual inspection while achieving the speed necessary for modern complex circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10303878B2Methods and apparatus for automatic detection and elimination of functional hardware trojans in IC designs
Publication Date: 2019.05.28 EASY LOGIC TECH LTD
  • US10303878B2 patent drawing
  • US10303878B2 patent drawing
  • US10303878B2 patent drawing

AI summary

A method detects, locates, and masks a hardware Trojan (HT) in an arithmetic circuit to improve circuit security. The method provides a first netlist and a second netlist of the arithmetic circuit, uses reverse engineering to extract 2-input XOR sub circuits, XOR trees, 1-bit adders, 1-bit adder graphs and arithmetic macros from the first netlist and the second netlist to obtain a first plurality of arithmetic macros and a second plurality of arithmetic macros, detects the HT by comparing the first plurality of arithmetic macros with the second plurality of arithmetic macros with functional ECO engine, locates the HT in the second netlist, and improves security of the arithmetic circuit by masking the HT with addition of a patch in the second netlist to obtain a patched netlist.