Hardware Trust Verification in Data Communication Systems

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Solution Overview

Problem

DMA systems in data communication networks, particularly those implementing Network Function Virtualization (NFV), have not been optimized to efficiently verify and report network-wide hardware trust, leading to inefficiencies in hardware-trust validation.

Innovation Solution

A data communication system comprising Network Interface Cards (NICs), Central Processing Units (CPUs), and Data Memory Buffers (DMBs) that execute hardware-trust software to assert control over APIs, receive and hash hardware-trust data with physically-embedded keys, and transfer results for validation, enabling efficient network-wide hardware-trust verification using a master NIC-based hierarchy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If DMA systems are used for user data transfers in NFV servers, then data transfer efficiency is improved, but hardware-trust verification efficiency deteriorates

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidhardware-trust validation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the hardware-trust verification process by introducing a master NIC that coordinates verification across multiple NICs, CPUs, and DMBs. Each component verifies trust independently using segmented challenge-response protocols, allowing parallel verification that doesn't block data transfer operations. This segmentation enables DMA systems to maintain both data transfer efficiency and hardware-trust verification efficiency.

Inventive Principle:
Principle #1Segmentation

2Reliability

If network-wide hardware-trust verification is implemented across all NICs, CPUs, and DMBs, then security reliability is improved, but system complexity increases

Engineering Contradiction:
Improvehardware-trust validationVSAvoidverification system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a master NIC as an intermediary that coordinates hardware-trust verification across the network. The master NIC receives challenge data, distributes it to slave NICs, CPUs, and DMBs, and aggregates verification results. This intermediary approach simplifies the verification system by centralizing coordination while allowing distributed execution, reducing overall system complexity while maintaining network-wide security reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If hardware-trust keys are physically embedded in all network components, then trust security is improved, but manufacturing cost increases

Engineering Contradiction:
Improvehardware-trust securityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal hardware-trust key architecture where the same cryptographic key type and verification protocol are used across NICs, CPUs, and DMBs. This universality allows standardized manufacturing processes and bulk provisioning of trust keys, reducing per-unit manufacturing costs while maintaining consistent security levels across all network components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for efficient verification of network-wide hardware trust with a single hardware-trust challenge, effectively maintaining hardware-trust across large and complex data communication networks, even in NFV server systems, by optimizing the DMA system for hardware-trust data handling.

Implementation Method 1

The data network components hash the random numbers with their secret hardware-trust keys and return the hardware trust results

Methodology Applied
Scientific EffectHashing:

Data Source

PatentUS9864856B2Efficient hardware trust verification in data communication systems that comprise network interface cards, central processing units, and data memory buffers
Publication Date: 2018.01.09 T MOBILE INNOVATIONS LLC
  • US9864856B2 patent drawing
  • US9864856B2 patent drawing
  • US9864856B2 patent drawing

AI summary

A data communication system comprises a Network Interface Card (NIC), Central Processing Unit (CPU), and Data Memory Buffer (DMB) to efficiently verify hardware-trust. The NIC, CPU, and DMB execute boot-up software, and in response, the NIC, CPU, and DMB execute hardware-trust software to assert control over their Application Programming Interfaces (APIs). The NIC, CPU, and DMB receive and hash hardware-trust data with their physically-embedded hardware-trust codes to generate hardware-trust results. The NIC, CPU, and DMB transfer their hardware-trust results for hardware-trust validation. The CPU may execute Network Function Virtualization Virtual Network Functions (NFV VNFs) for Software Defined Networks (SDNs).