High-Level Hardware Verification Patterns
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Solution Overview
Problem
Writing properties for hardware functionality verification in computer-aided design is challenging due to the need for implementation-level specifications, which complicates functional verification and reduces the benefits of computer-aided design, especially with complex hardware designs involving pipelining and concurrent subsystems.
Innovation Solution
The introduction of a computer translator that converts high-level properties into low-level code using a library of reusable and flexible modeling patterns, allowing designers to specify properties at a higher functional level without writing implementation code, and automatically generating code for verification tools like Accellera's Open Verification Library (OVL), enabling independent verification flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If designers write properties in terms of implementations, then verification can be performed, but the complexity of property specification increases and functional verification becomes difficult
Solution Approach 1:
The property specification is segmented into reusable patterns that can be independently defined and combined. Each pattern captures a specific verification concept (e.g., sequence, handshake, priority) that can be applied separately to different parts of the design, reducing the overall complexity of specification.
Solution Approach 2:
A computer translator acts as an intermediary between the high-level pattern-based specification and the low-level verification code. This translator automatically converts patterns into tool-specific assertion languages (OVL, SVA, PSL), eliminating the need for designers to manually write complex implementation-level properties.
2Reliability
If designers write low-level implementation code directly, then verification properties can be specified, but the amount of code increases and maintenance becomes difficult
Solution Approach 1:
Instead of writing unique low-level verification code for each property, the system uses reusable pattern templates that can be instantiated multiple times with different parameters. A single pattern definition serves as a template that generates the necessary verification code through parameterization, dramatically reducing code quantity.
Solution Approach 2:
Patterns are made flexible through parameters that can be adjusted to fit different verification scenarios. By changing parameter values (e.g., sequence length, signal names, timing constraints), the same pattern can verify different properties without requiring separate code implementations.
3Reliability
If verification properties are written at implementation level, then specific hardware behaviors can be verified, but the properties become tool-dependent and less flexible
Solution Approach 1:
The pattern library is designed to be universal and tool-independent. Patterns define verification logic at an abstract level that can be translated to multiple assertion languages (OVL, SVA, PSL) and used with different verification tools. This universality allows the same patterns to work across various toolchains while maintaining verification precision.
Solution Approach 2:
The computer translator serves as a mediator that handles tool-specific syntax and semantics. It converts tool-independent patterns into tool-specific assertion code, allowing designers to write portable specifications while achieving precise verification in the target tool environment.
4Reliability
If comprehensive verification properties are written manually, then all hardware functionalities can be verified, but the time and effort required increases significantly
Solution Approach 1:
Verification patterns are pre-defined and prepared in advance, capturing common verification scenarios and best practices. This preliminary action allows designers to leverage existing patterns for routine verification needs, significantly reducing the time and effort required to achieve comprehensive verification coverage.
Solution Approach 2:
The verification specification is divided into modular patterns that can be independently selected and combined based on the specific hardware being verified. This segmentation allows designers to efficiently construct comprehensive verification suites by assembling relevant patterns rather than writing everything from scratch.
Data Source
AI summary
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as pipelines and bus priorities. Such common features are specified only in high-level patterns and temporal properties to be verified. This is advantageous because less verification code to be written, automated synthesis of assertions enforces monitor-style of writing assertions rather than generator-style, and the high-level code can be seamlessly migrated to another verification tool by producing another code generator for the new assertion language.