Hardware Verification Unit for Secure Data Processing
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Solution Overview
Problem
Microprocessors are vulnerable to attacks and errors during instruction execution, leading to potential deviations from the desired instruction sequence, which can compromise information security and require effective detection mechanisms.
Innovation Solution
The implementation of a code flow control method using signature values to verify the integrity of instruction execution, where a processor directly accesses a hardware component to store and modify signature values, generating verification values to ensure correct function calls and detect any deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple high-level instructions are used to verify function execution, then verification completeness is improved, but instruction complexity and processing overhead increase
Solution Approach 1:
The patent extracts the verification logic from multiple high-level instructions and implements it as a dedicated hardware component (verification unit) that automatically checks function call integrity. This separates the verification function from the main instruction stream, maintaining completeness while reducing complexity.
Solution Approach 2:
The patent introduces signature values as intermediary data structures that represent function execution states. Instead of using multiple complex verification instructions, the system uses these signature intermediaries to simplify the verification process while maintaining thoroughness.
2Reliability
If multiple instructions are executed for verification, then detection capability is improved, but processing speed decreases
Solution Approach 1:
The patent replaces the mechanical execution of multiple software instructions with a hardware-based verification mechanism. The verification unit operates in parallel with the main processor, using hardware logic to perform detection functions that would otherwise require multiple sequential instructions, thereby maintaining detection capability while improving processing speed.
Solution Approach 2:
The patent computes and stores signature values in advance during function compilation and execution. This preliminary action allows the verification unit to perform rapid comparisons without requiring multiple instructions during critical execution paths, thus maintaining both detection capability and processing speed.
3Productivity
If hardware components are used for verification, then processing speed is improved, but device complexity increases
Solution Approach 1:
The verification unit is designed as a multi-functional hardware component that can handle multiple verification tasks using a unified architecture. It processes different types of function calls and signature comparisons through the same hardware structure, reducing overall hardware complexity while maintaining high processing speed.
Solution Approach 2:
The patent implements verification functionality locally within the processor architecture through a dedicated verification unit. This localized implementation allows the hardware to operate independently with simple, focused logic rather than requiring complex distributed verification mechanisms across the entire system.
4Reliability
If signature verification is implemented, then security is improved, but instruction execution time increases
Solution Approach 1:
The verification unit performs signature checks at periodic intervals corresponding to function call boundaries rather than continuously during instruction execution. This periodic verification approach maintains security by checking at critical points while minimizing interference with the execution time of individual instructions.
Solution Approach 2:
The patent uses signature values as simplified copies or representations of full function verification data. Instead of verifying complete function execution details, the system verifies compact signature values that represent the essential verification information, reducing the time required for security checks.
Data Source
AI summary
Described herein are embodiments that relate to a method for use in data processing. An embodiment includes providing an arithmetic unit configured to perform any one in a set of operations. An embodiment includes providing a control register configured to hold control data. An embodiment includes providing in the set of operations, a control operation to provide process control, the control operation to operate on an operand that is coupled to the control data. A system for use in data processing is also disclosed having process registers and a control register. Further, a non-transitory computer-readable medium storing instruction code thereon for use in data processing is disclosed. When executed, the code causes a control operation forming part of a set of operations to operate on an operand that is coupled to control data held in a control register.