Hardware Write Cache Engine for Storage Adapter Performance

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Solution Overview

Problem

Current storage adapter systems require significant CPU cycles for metadata updates in write caches, which can lead to performance bottlenecks and inefficiencies, particularly in managing cache destage rates and thresholds, often requiring firmware involvement.

Innovation Solution

A hardware write cache engine is implemented to manage storage write cache data and metadata with minimal or no firmware involvement, utilizing hardware acceleration to monitor cache levels and optimize destage rates and thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If CPU-based metadata updates are used for write cache management, then flexibility and control are maintained, but processing time and CPU cycle consumption increase significantly

Engineering Contradiction:

Improvemetadata update timeVSAvoidhardware automation level

Core Design Contradiction:

Loss of timeVSExtent of automation

Solution Approach 1:

The patent replaces the CPU-based mechanical processing system with a dedicated hardware write cache engine that uses parallel hardware circuits, state machines, and buffers to perform metadata updates and cache management operations independently of the CPU, thereby reducing processing time and CPU cycle consumption

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The write cache management functionality is segmented into separate hardware components including a write cache engine, metadata structures, LRU queues, and hash tables, allowing each component to operate independently and in parallel, which reduces the overall time required for cache management operations

Inventive Principle:

Principle #1Segmentation

2Productivity

If firmware involvement is required for cache management, then control and monitoring capabilities are maintained, but system performance and processing speed decrease

Engineering Contradiction:

Improvecache management processing speedVSAvoidfirmware involvement complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent substitutes firmware-based control with a fully hardware-implemented write cache engine that manages cache operations, monitors cache levels, and handles metadata updates through dedicated hardware circuits, eliminating the performance bottleneck introduced by firmware involvement

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware write cache engine is designed to autonomously manage write cache operations including metadata updates, LRU queue maintenance, and cache level monitoring without requiring external firmware intervention, thereby improving processing speed and reducing system complexity

Inventive Principle:

Principle #25Self-service

3Reliability

If comprehensive metadata structures are maintained for cache coherency, then data integrity and coherency are ensured, but CPU cycle consumption and processing overhead increase

Engineering Contradiction:

Improvecache coherencyVSAvoidCPU cycle consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces CPU-based metadata management with a hardware write cache engine that maintains cache coherency and manages metadata structures through dedicated hardware circuits, reducing CPU cycle consumption while ensuring data integrity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware engine performs preliminary actions by pre-managing metadata updates and cache coherency operations before they become critical, using hardware queues and buffers to prepare and process metadata changes efficiently, thereby reducing overall CPU cycle consumption

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10078595B2Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache

Publication Date: 2018.09.18 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine monitors cache levels used for managing cache destage rates and thresholds for destages from storage write cache substantially without using firmware for greatly enhancing performance.