Hardware XML Accelerator for Parsing Throughput and Security
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing XML processing solutions are inefficient due to software-based methods that require excessive string comparisons and monopolize processor resources, leading to bottlenecks in parsing and security processing, especially with increasing use of XML documents across distributed computing environments.
Innovation Solution
A hardware XML accelerator is implemented, comprising processors, hardware parser units, cryptographic units, and finite state machines, which processes XML documents in segments and applies security measures, reducing software processing overhead and latency by using direct memory access and ternary content addressable memory for efficient tokenization and validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based XML parsing is used, then compatibility and ease of implementation are maintained, but processing speed and processor resources are consumed excessively
Solution Approach 1:
The patent replaces software-based XML parsing mechanisms with dedicated hardware parsing circuits. The hardware parser uses finite state machines and content addressable memory to tokenize and validate XML documents, eliminating the need for software string comparisons and significantly improving processing speed while reducing processor time consumption.
Solution Approach 2:
The XML processing function is segmented into separate hardware modules: a hardware parser for tokenization and validation, a security processor for security operations, and a symbol table for reference. This segmentation allows each module to operate independently and efficiently, improving overall productivity without consuming excessive processor resources.
2Reliability
If security processing is applied to XML documents, then security validation is improved, but processing time and complexity increase
Solution Approach 1:
The patent merges XML parsing and security processing into a unified hardware accelerator. The hardware parser and security processor operate in close integration, with the parser feeding tokenized data directly to the security processor. This combining eliminates sequential processing delays and reduces overall processing time while maintaining comprehensive security validation.
Solution Approach 2:
The hardware parser performs preliminary tokenization and validation of XML documents before security processing. By pre-processing the document structure and identifying security-relevant elements in advance, the system reduces the processing time required for subsequent security validation operations.
3Productivity
If hardware XML accelerator is implemented, then processing throughput is improved, but device complexity increases
Solution Approach 1:
The hardware accelerator is designed with multi-functionality to justify its complexity. The same hardware platform handles XML parsing, tokenization, validation, and security processing operations. The shared memory space and integrated architecture allow a single device to perform multiple functions, improving throughput while managing complexity through consolidation rather than separate dedicated components.
Data Source
AI summary
A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.