Hard-Wired HSSI CRC Architecture for Stall-Free Packet Throughput
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Solution Overview
Problem
High-speed serial interface (HSSI) circuitry in programmable logic devices (PLDs) faces challenges in efficiently performing cyclic redundancy check (CRC) operations at high data rates, often requiring general-purpose logic to compute CRC, which can lead to stalling or increased inter-packet gaps, especially in advanced communication protocols with higher data rates and multiple lanes.
Innovation Solution
Incorporating CRC generation and checking circuitry into the hard-wired portion of PLDs, between the PLD core and HSSI transmitter/receiver, allowing for efficient CRC operations without stalling packets or increasing inter-packet gaps, and enabling partial programmability for various CRC functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CRC operations are performed in general-purpose PLD core circuitry, then the PLD can support various communication protocols, but packet stalling and increased inter-packet gaps occur at high data rates
Solution Approach 1:
The patent segments the PLD into distinct functional regions: general-purpose programmable logic core and dedicated hard-wired HSSI circuitry with integrated CRC units. This segmentation allows CRC operations to be performed in dedicated hardware independent of the programmable core, eliminating packet stalling while maintaining protocol versatility through the programmable core's configurability.
Solution Approach 2:
The patent introduces dedicated CRC generation and checking circuitry as intermediary components between the HSSI transmitter/receiver and the PLD core. These intermediary CRC units handle error checking operations in hardware, preventing them from becoming bottlenecks that would stall packet processing in the programmable logic core.
2Device complexity
If CRC operations are performed in general-purpose logic, then device complexity is reduced, but operation speed decreases due to stalling packets
Solution Approach 1:
The patent applies local quality by implementing CRC functionality with different architectural qualities in different locations: dedicated hard-wired CRC circuitry with optimized logic paths for high-speed operation in the HSSI section, while the PLD core retains general-purpose programmable logic. This localized optimization enables high-speed CRC operations without requiring the entire device to be hard-wired.
Solution Approach 2:
The patent transitions from a single-dimension architecture where all logic is programmable to a multi-dimensional architecture that combines hard-wired dedicated CRC units with programmable logic core. This dimensional change in architectural organization allows simultaneous achievement of high-speed dedicated CRC processing and flexible programmable logic functionality.
3Productivity
If hard-wired CRC circuitry is added to HSSI, then CRC operations can proceed without stalling, but device complexity increases
Solution Approach 1:
The patent merges the CRC generation and checking functions directly into the HSSI transmitter and receiver circuitry, respectively. This consolidation integrates error checking operations into the existing high-speed serial interface data path, enabling continuous packet processing without stalling while avoiding the need for separate standalone CRC processing units that would increase overall device complexity.
Data Source
AI summary
A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).