Hardwired Model Calculation Unit for Multilayer Perceptron

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Solution Overview

Problem

Physical models for complex systems, such as internal combustion engines, struggle with calculation accuracy and real-time processing demands, making data-based models with numerous nodes necessary, which require high processing capacity.

Innovation Solution

A hardwired model calculation unit is designed to efficiently calculate neuron layers of a multilayer perceptron model, utilizing a processor core, memory, and DMA unit to store and process input and output variables, reducing processing load and enabling real-time calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If data-based models with a large number of nodes are used to achieve sufficient modelling accuracy, then modelling precision is improved, but processing capacity requirements increase

Engineering Contradiction:
Improvemodelling accuracyVSAvoidprocessing capacity
Core Design Contradiction:
Measurement precisionVSPower

Solution Approach 1:

The model calculation unit is divided into multiple neuron layers, each processing a portion of the computational workload. The data memory area is segmented into input variable sections and output variable sections for each layer, allowing parallel and sequential processing that distributes the computational burden while maintaining high modelling accuracy through the collective operation of all layers

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from software-based sequential processing to hardware-based parallel processing by implementing the model calculation unit as a dedicated hardware component with multiple neuron layers that can simultaneously process multiple computations, effectively adding a dimensional aspect to the processing architecture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If a separate hardwired model calculation unit is implemented, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improvecalculation speedVSAvoidhardware structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The model calculation unit is designed as a universal hardware component that can calculate multiple different neuron layers of a multilayer perceptron model. The data memory area can store input and output variables for any number of layers, and the processor core can be instructed via DMA to calculate different configurations, making the hardware structure adaptable to various model requirements without requiring dedicated hardware for each specific layer configuration

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The DMA unit acts as an intermediary between the microprocessor and the model calculation unit, handling the instruction and data transfer automatically. This mediator allows the complex hardware operations to be controlled through simple software commands, reducing the apparent complexity for the host system while enabling high-speed hardware-based calculations

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11449737B2Model calculation unit and control unit for calculating a multilayer perceptron model with feedforward and feedback
Publication Date: 2022.09.20 ROBERT BOSCH GMBH
  • US11449737B2 patent drawing
  • US11449737B2 patent drawing
  • US11449737B2 patent drawing

AI summary

A model calculation unit for calculating a multilayer perceptron model, the model calculation unit being designed in hardware and being hardwired, including: a process or core; a memory; a DMA unit, which is designed to successively instruct the processor core to calculate a neuron layer, in each case based on input variables of an assigned input variable vector and to store the respectively resulting output variables of an output variable vector in an assigned data memory section, the data memory section for the input variable vector assigned to at least one of the neuron layers at least partially including in each case the data memory sections of at least two of the output variable vectors of two different neuron layers.