Hardwired Remapped Memory for Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices, such as NAND or NOR flash memories, SRAM, and phase-change memory, experience gradual deterioration leading to increasing read and write errors, which can be difficult to correct as error rates rise, potentially causing system failures.
Innovation Solution
Implementing a hardware-based remapping process that redirects read/write signals from error-prone memory locations to spare, functioning areas within the memory device, using error correction codes to determine when to retire faulty memory cells and maintain overall system capacity without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to correct read/write errors, then reliability is improved, but device complexity increases and error correction becomes difficult or impossible as error rates increase
Solution Approach 1:
The patent applies preliminary action by proactively monitoring error rates in memory cells and retiring faulty cells before they cause system failures. The system continuously tracks error counts and triggers remapping operations in advance, preventing the accumulation of errors that would make correction impossible. This proactive approach maintains reliability while avoiding the complexity of correcting high-rate errors.
Solution Approach 2:
The patent extracts the faulty memory cells from the operational array by implementing a remapping mechanism that isolates and removes error-prone cells. When a cell exceeds its error threshold, it is logically retired and replaced with a spare cell, extracting the problematic element from the system while maintaining overall functionality. This separation simplifies the error correction process by removing the source of errors rather than attempting to correct them.
2Reliability
If memory cells are replaced to maintain capacity, then reliability is improved, but loss of time occurs during the remapping process
Solution Approach 1:
The patent implements self-service by enabling the memory device to automatically monitor its own health, detect errors, and perform remapping operations without external processor intervention. The system includes built-in error detection circuits and control logic that autonomously manage cell retirement and replacement, eliminating the need for time-consuming manual intervention while maintaining reliability.
Solution Approach 2:
The patent ensures continuity of useful action by designing the remapping process to occur transparently in the background during idle periods or low-activity moments. The system maintains continuous operation by performing error monitoring and cell replacement during non-critical time windows, so that the remapping process does not interrupt normal memory operations. This allows the memory device to maintain capacity and reliability while minimizing time loss.
3Productivity
If hardware switching is used to redirect data paths, then productivity is improved through on-the-fly remapping, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary hardware switching mechanism that acts as a mediator between the memory controller and the memory array. This switching component enables on-the-fly remapping by redirecting data paths to spare cells without requiring complex software intervention. The intermediary hardware layer handles the complexity of path redirection, allowing fast productivity improvement while the higher-level system remains simple and unaware of the underlying complexity.
Data Source
AI summary
Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.