Harmonic Rejection Mixer Switching for Low-Noise LO Suppression
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Solution Overview
Problem
Harmonic rejection mixers in existing technologies suffer from poor noise performance, high local oscillator driver power consumption, large silicon area requirements, and complex layouts due to high transistor switching numbers, along with complicated calibration processes for harmonic suppression.
Innovation Solution
A harmonic rejection mixer unit with at least two transistor units that generate transistor control signals from a local oscillator signal with a duty cycle of less than 50%, ensuring constructive summation of output signals and avoiding destructive cancellation, along with a conversion gain modulating means for voltage-to-current conversion to improve noise performance and reduce transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a harmonic rejection mixer uses multiple transistor units to suppress LO harmonics, then harmonic rejection performance is improved, but noise performance deteriorates and device complexity increases
Solution Approach 1:
The mixer is divided into multiple parallel transistor units (first, second, third, and fourth transistor units) with different duty cycles. Each unit processes a portion of the signal with tailored switching characteristics, allowing harmonic rejection through constructive interference while maintaining low noise by optimizing each segment's contribution to the output signal.
Solution Approach 2:
Each transistor unit is assigned a specific duty cycle (50%, 25%, 12.5%, etc.) that creates distinct local signal characteristics. The first transistor unit operates at 50% duty cycle for fundamental mixing, while subsequent units operate at progressively lower duty cycles to selectively suppress specific harmonics, giving each part of the system a specialized function.
2Measurement precision
If a harmonic rejection mixer uses multiple transistor units to suppress LO harmonics, then harmonic rejection performance is improved, but device complexity and silicon area increase
Solution Approach 1:
Multiple transistor units with different duty cycles are merged into a single parallel structure that processes the same input signal simultaneously. The units are combined such that their outputs are summed at the operational amplifier inputs, achieving harmonic rejection through signal interference patterns rather than through complex sequential processing.
Solution Approach 2:
The transistor units operate with periodic switching at different duty cycles (50%, 25%, 12.5%, etc.) that are integer divisions of each other. This periodic action with harmonically related duty cycles creates predictable interference patterns that suppress specific LO harmonics while maintaining the fundamental mixing function.
3Measurement precision
If a harmonic rejection mixer uses multiple transistor units to suppress LO harmonics, then harmonic rejection performance is improved, but local oscillator driver power consumption increases
Solution Approach 1:
Instead of using all transistor units at full power continuously, the invention employs units with progressively reduced duty cycles (50%, 25%, 12.5%, etc.). This partial action approach allows the later units to operate at lower power levels since they only need to contribute to suppressing specific harmonic components rather than the full signal, reducing total LO driver power requirements.
4Measurement precision
If a harmonic rejection mixer uses multiple transistor units to suppress LO harmonics, then harmonic rejection performance is improved, but calibration complexity increases
Solution Approach 1:
The invention uses fixed duty cycle ratios (50%, 25%, 12.5%, etc.) as design parameters that are determined during manufacturing rather than requiring post-manufacturing calibration. These parameter changes are built into the transistor unit switching schemes, eliminating the need for complex calibration loops and simplifying the manufacturing process while maintaining harmonic rejection performance.
Data Source
AI summary
A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of <50% and are generated such that the shape of the multiplication signal ELO) is achieved by a constructive summation of the output signals from the transistor units (T3a, T3b; T4a, T4b). The transistor control signals (GS1-GS4) are generated such that only a summation of output signals from the transistor units with the same sign or with zero is performed.