Harmonic Task Interrupt Switch for Multicore Processor Scheduling
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Solution Overview
Problem
Managing tasks in multicore or multiprocessor computer systems is complex and time-consuming due to the non-polynomial nature of optimizing task distribution among processor units, even with real-time operating systems.
Innovation Solution
A computer system with synchronous processor units that access resources in a non-concurrent manner, utilizing a task interrupt switch device to reorder tasks by increasing periods, prioritizing shorter tasks and distributing them based on priority and usage, ensuring efficient execution through a harmonic task set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If real-time operating systems are used to optimize task distribution among processor units, then task execution efficiency is improved, but system complexity and management overhead increase
Solution Approach 1:
The patent segments the task distribution problem into two parts: (1) static harmonic task set definition with predetermined periods and priorities, and (2) simple runtime scheduling based on periodic interrupts. This segmentation allows complex optimization to be done offline, leaving only simple periodic execution decisions at runtime, thereby reducing real-time management complexity while maintaining execution efficiency.
Solution Approach 2:
The patent performs preliminary action by pre-defining the harmonic task set with predetermined periods, priorities, and processor assignments before runtime. The task distribution optimization is completed in advance, allowing the runtime system to simply follow the pre-established schedule without complex real-time decision-making, thus improving execution efficiency while minimizing runtime complexity.
2Productivity
If complex task distribution optimization is performed to achieve best possible distribution, then task execution performance is improved, but time consumption for management increases
Solution Approach 1:
The patent performs the complex task distribution optimization as a preliminary action during system configuration or initialization, rather than during runtime. The harmonic task set is pre-optimized and stored, allowing fast runtime execution without repeated complex calculations, thus improving performance while minimizing time consumption during actual task management.
Solution Approach 2:
The patent implements periodic action through fixed-period task execution based on predetermined harmonic periods. Tasks are executed at regular intervals defined by their periods, eliminating the need for continuous complex scheduling decisions. This periodic structure simplifies runtime management to simple interrupt-driven execution, reducing time consumption for task management while maintaining optimal performance.
3Productivity
If tasks are distributed dynamically among processor units to balance load, then system utilization is improved, but scheduling complexity increases
Solution Approach 1:
The patent segments scheduling complexity by separating task definition (static, harmonic periods and priorities) from task execution (dynamic, interrupt-driven). The static portion defines the optimal distribution pattern, while the dynamic portion simply follows this pattern through periodic interrupts. This segmentation achieves good system utilization through harmonic task sets while keeping actual scheduling simple and deterministic.
Solution Approach 2:
The patent uses parameter changes by defining tasks with specific harmonic period parameters that are integer multiples of each other. This parameter relationship ensures that tasks naturally synchronize and distribute evenly across processors without complex scheduling logic. The harmonic period parameters automatically enforce balanced utilization while simplifying the scheduling mechanism to simple periodic execution.
Data Source
AI summary
A computer system comprising a plurality of processor units, resources for executing a harmonic set of tasks, and a task interrupt switch device having inputs for receiving a common time base and the task interrupts, outputs each connected to a respective one of the processor units, registers each corresponding a to respective one of the outputs, reinitializable counters each corresponding to a respective one of the outputs, and a control unit arranged to distribute the task interrupts between the outputs as a function of the values of the registers and of the counters.