Hardware Accelerated Reconfigurable Processors for Database Query Scheduling

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Solution Overview

Problem

General purpose CPUs are inefficient for database applications due to inaccurate branch prediction, limited parallelism, and inadequate memory and I/O bandwidth, leading to performance bottlenecks in relational database systems.

Innovation Solution

A custom computing solution with Hardware Accelerated Reconfigurable Processors (HARPs) that offload repetitive database operations, utilizing dataflow architecture and column-store format to optimize database processing, and a run-time scheduler that allocates resources and dispatches tasks efficiently across hardware and software execution resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general purpose CPUs are used to execute database queries, then flexibility and programming language compatibility are maintained, but processing efficiency and performance deteriorate due to inaccurate branch prediction and limited parallelism

Engineering Contradiction:

Improveprogramming language compatibilityVSAvoidquery processing efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces the mechanical CPU instruction execution system with a hardware-based dataflow processing system. Database operations are translated into dataflow graphs that are executed by specialized hardware processors, substituting the software-based CPU mechanism with a hardware accelerator that natively processes database operations more efficiently.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent segments database operations into distinct dataflow graph nodes representing different operations (scanning, filtering, joining, aggregating). This segmentation allows each operation to be optimized independently and executed in parallel on specialized hardware, improving overall processing efficiency while maintaining SQL compatibility through the translation layer.

Inventive Principle:

Principle #1Segmentation

2Speed

If branch prediction and speculative execution are used to keep CPU pipeline busy, then instruction execution speed is improved, but reliability deteriorates due to data-dependent prediction accuracy

Engineering Contradiction:

Improveinstruction execution speedVSAvoidbranch prediction accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

Instead of predicting branch outcomes and executing speculatively (CPU approach), the patent inverts the approach by using a hardware dataflow system that processes data independently of control flow predictions. The dataflow graph executes operations in parallel without relying on branch prediction, achieving both speed and reliability by eliminating the speculative execution mechanism entirely.

Inventive Principle:

Principle #13The other way round (Inversion)

3Productivity

If simultaneous multithreading and multi-core processing are employed, then parallel processing capability is improved, but device complexity increases due to manual parallelism creation requirements

Engineering Contradiction:

Improveparallel processing capabilityVSAvoidapplication code modification complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service parallelism where the dataflow graph automatically partitions and distributes operations across multiple hardware processors without requiring manual intervention. The system self-manages thread creation, scheduling, and load balancing, eliminating the need for application developers to manually create parallelism while achieving high parallel processing capability.

Inventive Principle:

Principle #25Self-service

4Speed

If code-flow architecture with pipelined instruction flow is used, then instruction execution efficiency is improved, but productivity deteriorates due to limited register files and ineffective on-chip cache for large database workloads

Engineering Contradiction:

Improveinstruction execution efficiencyVSAvoiddata processing throughput

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The patent transitions from a one-dimensional instruction pipeline (Von Neumann architecture) to a two-dimensional dataflow architecture where data flows through multiple parallel processing paths simultaneously. This dimensional change enables massive parallelism and eliminates the register file bottleneck by using hardware-based dataflow that processes gigabytes to terabytes of data through parallel data paths rather than sequential instruction execution.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9424315B2Methods and systems for run-time scheduling database operations that are executed in hardware

Publication Date: 2016.08.23 TERADATA US INC

AI summary

Embodiments of the present invention provide a run-time scheduler that schedules tasks for database queries on one or more execution resources in a dataflow fashion. In some embodiments, the run-time scheduler may comprise a task manager, a memory manager, and hardware resource manager. When a query is received by a host database management system, a query plan is created for that query. The query plan splits a query into various fragments. These fragments are further compiled into a directed acyclic graph of tasks. Unlike conventional scheduling, the dependency arc in the directed acyclic graph is based on page resources. Tasks may comprise machine code that may be executed by hardware to perform portions of the query. These tasks may also be performed in software or relate to I/O.