HARQ Combiner Cache Memory Hierarchy for Chip Area Reduction
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Solution Overview
Problem
The existing HARQ memory solutions in wireless communication technologies, such as HSDPA and LTE, face challenges in reducing chip area and power consumption, especially with increasing data rates, as they require large memory spaces that increase chip area and power consumption when using SRAM or off-chip SDRAM.
Innovation Solution
A method and HARQ combiner that utilize a Cache to store HARQ data, allowing for a hierarchy memory structure with on-chip Cache and off-chip DDR/SDRAM, dynamically managing memory space by using Cache line replacement algorithms based on CRC results to reduce the need for external memory access and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large SRAM is used to store HARQ information for high data velocity, then the memory capacity is sufficient, but the chip area increases
Solution Approach 1:
The patent segments the HARQ memory into two parts: on-chip SRAM for storing critical HARQ soft bits and off-chip SDRAM for storing less frequently accessed data. This segmentation allows the system to maintain sufficient total memory capacity while reducing the area occupied by expensive on-chip SRAM, thereby resolving the contradiction between memory capacity and chip area.
Solution Approach 2:
The patent introduces a hierarchical memory architecture that adds a spatial dimension to memory organization by placing different types of memory (SRAM and SDRAM) at different locations (on-chip and off-chip). This dimensional change allows the system to optimize both area usage and memory capacity by strategically placing data in the most appropriate memory location based on access patterns.
2Area of stationary object
If off-chip SDRAM is used to reduce chip area, then the chip area is reduced, but the bandwidth consumption and power consumption increase
Solution Approach 1:
The patent uses on-chip SRAM to preliminarily store HARQ soft bits that require frequent access. By pre-positioning frequently accessed data in the faster, lower-power on-chip SRAM, the system reduces the need for subsequent off-chip memory accesses, thereby reducing both bandwidth consumption and power consumption while maintaining reduced chip area.
Solution Approach 2:
The patent applies different memory qualities to different data based on their access characteristics. Frequently accessed HARQ soft bits are stored in high-speed on-chip SRAM, while less frequently accessed data is stored in off-chip SDRAM. This local quality differentiation optimizes the balance between chip area and power consumption by ensuring that each piece of data resides in the memory type that best suits its access pattern.
3Quantity of substance
If a large SRAM is used to store HARQ information, then the memory capacity is sufficient, but the manufacturing cost increases
Solution Approach 1:
The patent segments the memory architecture into on-chip SRAM and off-chip SDRAM components. This segmentation allows the system to use a smaller, less expensive on-chip SRAM for critical data while utilizing the more cost-effective off-chip SDRAM for additional storage capacity, thereby reducing overall manufacturing cost while maintaining sufficient memory capacity.
Solution Approach 2:
The on-chip SRAM acts as an intermediary between the processor and the off-chip SDRAM. It caches frequently accessed HARQ soft bits, reducing the need for direct access to the larger off-chip memory. This intermediary approach allows the system to achieve sufficient effective memory capacity using a smaller combination of memory types, reducing manufacturing costs compared to using a single large SRAM.
Data Source
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AI summary
The invention provides a method for storing hybrid automatic repeat request (HARQ) data, the method including: when receiving new data of a coded block, a HARQ processor writing the new data into a high rate buffer memory (Cache) and a channel decoder; the Cache writing the new data into a data memory of the Cache or an external memory; and when receiving retransmitted data of the coded block, the HARQ processor obtaining a previous data corresponding to the retransmitted data from the data memory of the Cache or the external memory through the Cache, combining the retransmitted data and the previous data, and writing the combined data to the Cache and the channel decoder; the Cache writing the combined data into the data memory of the Cache or the external memory. The invention also provides a HARQ combiner. The invention is very beneficial in reducing the chip area and power consumption and improving the competitiveness.