HARQ Memory Hierarchy Management for Power Reduction
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Solution Overview
Problem
The existing HARQ memory solutions face challenges in reducing chip area and power consumption, particularly in high-speed data transmission technologies like LTE, where large SRAMs are required, leading to increased chip area and power consumption.
Innovation Solution
A method for hierarchy management that utilizes on-chip memory with overwriteable storage blocks, dynamically assigning storage between on-chip SRAM and off-chip DDR/SDRAM, where new data is stored in on-chip memory if available, and off-chip memory if not, with status bits indicating overwriteability and updating based on data integrity checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large on-chip SRAM is used to store HARQ information for high-speed data transmission, then the memory capacity is sufficient, but the chip area increases significantly
Solution Approach 1:
The patent divides the HARQ memory into multiple storage blocks (e.g., 4 blocks of 64K bits each in LTE Category 3) within the on-chip SRAM. This segmentation allows the system to manage limited on-chip resources efficiently while providing sufficient total storage capacity through hierarchical management with off-chip memory.
Solution Approach 2:
The patent implements a nested memory hierarchy where on-chip SRAM storage blocks are nested within a larger off-chip SDRAM memory system. The on-chip blocks serve as fast access buffers for frequently used HARQ data, while off-chip memory provides extended capacity for less frequently accessed data, creating a nested structure that optimizes both speed and capacity.
2Area of stationary object
If off-chip SDRAM is used to reduce chip area, then the chip area is reduced, but the bandwidth consumption and power consumption increase
Solution Approach 1:
The patent assigns different quality levels to different storage blocks based on their usage patterns. Frequently accessed HARQ data is stored in on-chip SRAM blocks with fast access and low power consumption, while less frequently accessed data is stored in off-chip SDRAM. This local quality differentiation optimizes the overall power consumption by keeping hot data in low-power on-chip memory.
Solution Approach 2:
The patent uses preliminary actions such as pre-fetching and pre-positioning of HARQ data in on-chip storage blocks before they are needed. By anticipating future access patterns and pre-loading data into on-chip memory, the system reduces the frequency of off-chip memory accesses, thereby reducing bandwidth consumption and power consumption.
3Speed
If on-chip memory is used for storing new data, then the access speed is fast, but the memory fills up quickly requiring frequent overwriting
Solution Approach 1:
The patent implements dynamic memory management where storage blocks can be dynamically allocated, accessed, and overwritten based on real-time HARQ process requirements. The controller dynamically tracks which blocks are available for writing and manages the overwriting process based on data age and importance, providing adaptive memory management that optimizes access speed while handling limited capacity.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between the HARQ processing logic and the physical storage blocks. This controller manages the complexity of memory allocation, tracking which blocks are free for writing, handling overwriting decisions, and coordinating between on-chip and off-chip memory. By isolating the complexity in the controller layer, the system maintains fast access speeds while managing memory full conditions efficiently.
Data Source
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AI summary
The invention provides a method for hierarchy management for a hybrid automatic repeat request (HARQ) memory, wherein, the HARQ memory includes an on-chip memory including one or more storage blocks, each of which corresponds to a using status bit for indicating whether the storage block is overwriteable. The method includes the following steps of: when receiving new data of a coded block, searching the on-chip memory for any overwriteable storage block, and if there exists an overwriteable storage block, storing the new data of the coded block into the storage block and setting the using status bit corresponding to the storage block to be un-overwriteable; if there is no overwriteable storage block, storing the new data of the coded block into an off-chip memory; and when the new data of the coded block are checked and pass the check, setting the using status bit corresponding to the storage block in which the new data of the coded block are stored to be overwriteable. The invention also provides a corresponding system. The scheme disclosed in the invention reduces power consumption.