HARQ Combining and Rate Recovery With Single-Buffer LLR Processing
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Solution Overview
Problem
Existing wireless communication systems face challenges in managing memory resources efficiently for rate recovery and HARQ combining processes in 5G New Radio Physical Downlink Shared Channel (PDSCH) and Physical Uplink Shared Channel (PUSCH) due to the need for larger memory requirements at the receiver, which is scarce in Field Programmable Gate Arrays (FPGAs) and digital signal processor (DSP) chipsets.
Innovation Solution
A system and method that utilizes a single buffer for de-interleaving, bit-de-selection, and filler bit addition stages, storing LLRs row-wise and streaming out most significant bits (MSB) across rows, using a predetermined number of LLR data bits based on a start offset and redundancy version index, to optimize memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate buffers are used for de-interleaving, de-selection, and incremental redundancy based HARQ combining stages, then processing reliability is improved, but memory requirement increases significantly
Solution Approach 1:
The patent merges three separate buffer structures (de-interleaving buffer, de-selection buffer, and HARQ combining buffer) into a single unified buffer. This buffer is shared across all three functional stages, reducing total memory requirement from nG bits (separate buffers) to significantly less while maintaining processing reliability through proper buffer management and data flow control.
Solution Approach 2:
The unified buffer serves multiple functions simultaneously: it acts as de-interleaving buffer, de-selection buffer, and HARQ combining buffer. This multi-functional design allows the same memory resource to be reused across different processing stages, optimizing memory utilization without compromising any individual function's reliability requirements.
2Measurement precision
If full N number of LLRs are processed during HARQ combining, then decoding accuracy is improved, but latency and power consumption increase
Solution Approach 1:
The patent extracts and processes only the necessary subset of LLRs (dataLength number of LLRs) from the full N LLRs during HARQ combining. By identifying and processing only the relevant LLRs required for successful decoding, the system reduces processing latency and power consumption while maintaining decoding accuracy through selective processing of critical data.
Solution Approach 2:
The patent applies partial action by processing a limited number of LLRs (dataLength) rather than all N LLRs. This partial processing approach is sufficient to achieve successful decoding in most cases, reducing overall processing time and energy consumption while maintaining adequate decoding accuracy for practical communication scenarios.
3Quantity of substance
If a single buffer is used for all rate recovery sub-stages, then memory utilization is optimized, but device complexity increases
Solution Approach 1:
The patent segments the unified buffer into three distinct functional regions: de-interleaving buffer portion, de-selection buffer portion, and HARQ combining buffer portion. Each region is managed independently with specific data flow control, allowing the system to optimize memory utilization through sharing while maintaining functional clarity and reducing complexity through structured organization.
Data Source
AI summary
The present disclosure provides a system and a method for implementing rate recovery in the PUSCH and PDCH bit rate processing chain of network. The system packs log likelihood ratios (LLRs) data in such a way that for each equalized in phase and quadrature (IQ) symbols, a predetermined number of LLRs equal to the modulation order are packed. The system de-interleaves the packed LLRs by reading the most significant bit (MSB) LLRs row wise for the number of columns equal to the modulation order. The system uses a single buffer for de-interleaving, bit-deselection, and filler bit addition stages, thereby reducing memory requirement of the system. The system processes only a predetermined number of LLRs to a HARQ combining stage to optimize memory and reduce latency.