Harvard RISC Debug Access to Instruction Memory
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Solution Overview
Problem
Debugging in Harvard architecture processors is difficult due to the inability to access instruction memory, and existing modifications compromise robustness and performance.
Innovation Solution
A debug module that allows access to instruction memory through the data bus during debug mode, using a unified memory space with address remapping, while maintaining separate memory spaces during normal execution for robustness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate instruction memory and data memory are used in Harvard architecture, then robustness against data-overwriting-code is improved, but ease of debugging deteriorates
Solution Approach 1:
The system dynamically switches between execution mode and debug mode. In execution mode, separate instruction and data memory spaces are maintained for robustness. In debug mode, the memory spaces are unified to allow debugging access. This dynamic reconfiguration resolves the contradiction by adapting the memory architecture to the current operational requirements.
Solution Approach 2:
The memory address space configuration is changed based on operational mode. During normal execution, the processor operates with separate instruction and data address spaces. During debugging, the address space parameters are modified to allow unified access, enabling debuggers to read and write instruction memory while maintaining separate access during normal operation for robustness.
2Reliability
If instruction memory is made inaccessible during normal execution, then protection of instruction memory is improved, but accessibility for debugging deteriorates
Solution Approach 1:
The accessibility of instruction memory is dynamically controlled based on the operational mode. A mode indicator signal determines whether the system is in execution mode or debug mode. In execution mode, instruction memory remains protected and inaccessible to data bus operations. In debug mode, the mode indicator enables the instruction memory to be accessed through the data bus, allowing debugging operations while maintaining protection during normal execution.
Solution Approach 2:
A debug module acts as an intermediary between the debugger and the instruction memory. This module includes a mode indicator that tracks the operational state and controls access permissions. The intermediary enables controlled access during debugging while maintaining strict protection during normal execution, resolving the contradiction between protection and accessibility.
3Productivity
If separate buses for instruction and data are used, then simultaneous access performance is improved, but device complexity increases
Solution Approach 1:
The data bus is designed to serve multiple functions: it handles both data transmission during normal execution and instruction memory access during debugging operations. This multi-functionality reduces the need for completely separate bus structures while maintaining the performance benefits of simultaneous access capability through the mode-dependent routing controlled by the mode indicator.
Data Source
AI summary
A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux disconnects an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load/store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.