Hash-Based Hierarchical IC Layout Comparison
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Solution Overview
Problem
The increasing complexity and density of integrated circuit (IC) layouts pose challenges in efficiently managing and processing a large number of geometric shapes, requiring improved layouting techniques to ensure optimal performance and manufacturability.
Innovation Solution
The use of hierarchical IC layouts and a hash-based method to efficiently generate and compare hash codes of geometric transformations, allowing for rapid validation of hierarchy manipulation algorithms and reducing computing resources needed for layout comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical IC layout methods are used to manage complex circuits, then layout organization and structure are improved, but computing time for layout comparison increases from minutes to hours
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing hash codes for each cell during the hierarchical layout creation process. When layout comparison is needed, these pre-stored hash codes are retrieved and compared directly, rather than computing hash codes from scratch during comparison. This preliminary preparation significantly reduces the computing time required for layout verification while maintaining the benefits of hierarchical organization.
2Manufacturing precision
If detailed geometric transformations are applied to cells during instantiation, then layout precision is improved, but computing resources required for validation increase
Solution Approach 1:
The patent replaces the traditional mechanical approach of physically comparing detailed geometric transformations with a computational hash-based verification system. Instead of performing complex geometric calculations and comparisons during layout validation, the system uses hash functions to generate compact representations of cell instances and compares these hash values. This substitution dramatically reduces computing resources while maintaining verification accuracy.
Solution Approach 2:
The patent changes the parameter representation from detailed geometric coordinates and transformation matrices to compact hash code values. By transforming the comparison task from operating on high-dimensional geometric parameters to comparing low-dimensional hash values, the system maintains precision verification while significantly reducing computational complexity and resource consumption.
Data Source
AI summary
The apparatuses for IC layouting comprise interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to obtain a first hierarchical IC layout comprising a first instance of a cell. The cell from which the first instance is derived comprises at least one planar geometric shape representing components of a first IC. The first instance of the cell results from applying a first geometrical transformation operation to the cell during a first instantiation of the cell. Further the processing circuitry is configured to: generate a first hash code of the cell based on a hash function; and generate a second hash code of the first instance of the cell by applying a first mathematical operation to the first hash code. The first mathematical operation is corresponding to the first geometrical transformation operation applied to the cell.