Hash CAM Bus and Block Layout for Lower-Power Packet Classification
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Solution Overview
Problem
Ternary Content Addressable Memory (TCAM) devices require large die area and high power consumption due to the large number of transistors needed to store one bit of data, which results in significant heat dissipation and inefficiencies in packet forwarding and classification operations.
Innovation Solution
The Hash Content Addressable Memory (HCAM) system uses a hash function to calculate the location of stored search values, allowing for efficient match detection and reducing the number of active transistors during searches by distributing table entries across multiple hash CAM blocks based on shared masks, thereby minimizing power consumption and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TCAM is used to store packet classification rules, then packet forwarding and classification operations can be performed, but the die area per storage bit becomes large due to requiring 16 transistors per bit
Solution Approach 1:
The patent segments the TCAM into multiple banks, where each bank contains multiple arrays. This segmentation allows the system to distribute the storage burden and enables more efficient memory access patterns, reducing the effective die area required per functional bit while maintaining the same storage capacity and packet classification performance.
2Speed
If all compare logic transistors in all TCAM cells are activated simultaneously to search for a value, then match detection can be performed across all rows, but power consumption and heat dissipation increase significantly
Solution Approach 1:
By dividing the TCAM into multiple banks with separate compare logic units, the system can perform parallel searches across banks while activating fewer transistors per bank simultaneously. This segmentation enables the search function to be distributed, maintaining high search speed through parallelism while reducing peak power consumption in any single bank compared to activating all transistors in a monolithic TCAM.
Solution Approach 2:
The patent implements dynamic control of compare logic activation across different banks based on search requirements. Not all banks need to be fully activated for every search operation, allowing the system to dynamically adjust the number of active transistors to match the actual search needs, thereby reducing unnecessary power consumption while maintaining search capability.
3Reliability
If TCAM cells use two SRAM cells with 6 transistors each plus 4 transistors for comparison logic, then one bit of data can be stored, but the transistor count per bit becomes 16 which is inefficient
Solution Approach 1:
The patent merges the storage and comparison functions into a more integrated architecture where multiple bits are handled collectively across banks and arrays. Instead of treating each bit independently with its own full SRAM cell and comparison logic, the system combines resources across multiple cells to achieve the same functional reliability with reduced per-bit transistor overhead.
Data Source
AI summary
A hash content addressable memory system includes a hash content addressable memory block (HCB) that is a physical subsystem of the hash content addressable memory system. The first HCB include first bus select logic. The first bus select logic is connected to a plurality of key buses and to a plurality of operation buses. Each key bus from the plurality of key buses and each operation bus from the plurality of operation buses is connected to one and only one client in a plurality of clients. Every client in the plurality of clients is connected to only one key bus from the plurality of key buses and is connected to only one operation bus from the plurality of operation buses.