Hash Table and CAM Hybrid for Wire-Speed Packet Processing
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Solution Overview
Problem
Existing communication devices face inefficiencies and high costs in processing data packets due to collisions in hash-based search mechanisms, particularly when dealing with large control information fields, and require cost-effective solutions that operate at wire-speed without blocking incoming data packets.
Innovation Solution
The method involves applying multiple hash functions to generate multiple hashed values, which are used to access a group of hash tables stored in dynamic memory units, managing collisions through staggered access and additional solutions like chaining or using a content addressable memory (CAM), and associating keys with vacant entries in these tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a content addressable memory (CAM) is used to store the first data structure, then data packet processing speed is improved, but device cost increases significantly
Solution Approach 1:
The patent divides the search function into two parts: a hash table for quick indexing and a CAM for collision resolution. This segmentation allows the system to use a smaller, cheaper CAM only when needed, rather than using a large CAM for all searches, thus reducing overall cost while maintaining high processing speed.
Solution Approach 2:
The hash table acts as an intermediary between the data packet processing function and the CAM. It pre-processes the search key by hashing it, which reduces the number of direct CAM queries needed and minimizes collisions, thereby reducing the size and cost of the CAM required.
2Speed
If SRAM is used to store the first data structure, then processing speed is improved, but device cost increases
Solution Approach 1:
The patent uses a hash table with standard memory (not expensive SRAM) to store the first data structure. This hash table is updated periodically but doesn't require the high speed or high cost of SRAM, as it serves as an intermediary rather than the final storage for active processing.
3Productivity
If VLSI area is consumed for on-chip memory storage, then processing efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent moves the storage of the first data structure from on-chip VLSI memory to off-chip memory, utilizing the memory dimension rather than the physical chip area dimension. This reduces the VLSI area consumption on the chip while maintaining processing efficiency through the hash table's quick access capabilities.
4Quantity of substance
If hash function mapping is applied to reduce memory space, then memory utilization is improved, but collision rate increases
Solution Approach 1:
The patent converts the harmful effect of hash collisions into a beneficial feature by using the CAM to resolve collisions. Instead of trying to eliminate collisions through complex hashing, the system embraces them and uses the CAM's parallel search capability to handle multiple collisions simultaneously, improving overall system reliability.
Solution Approach 2:
The patent creates a composite memory system combining hash table and CAM technologies. The hash table provides efficient indexing and space utilization, while the CAM provides collision resolution and parallel search capability, creating a hybrid system that achieves both memory efficiency and high reliability.
Data Source
AI summary
A device and a method for processing a data packet. The method includes: receiving a key, applying multiple hash functions to provide multiple hashed values; accessing a group of hash tables using the multiple hashed values; associating between the key and an accessed vacant entry of an hash table out of the group of has tables. The device includes a communication controller connected to at least one memory bank; wherein the communication controller is adapted to receive a key associated with a data packet, apply multiple hash functions to provide multiple hashed values; access a group of hash tables stored within the at least one memory bank, using the multiple hashed values; and determine a data packet processing operation in response to a content of accessed entries of the multiple hash tables.