Hash Circuit Memory Bank Access Coordination
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Solution Overview
Problem
In Ethereum's proof-of-work (PoW) process, the sequential access to different memory banks by hash computation circuits leads to bank access conflicts, reducing memory access efficiency and limiting the use of memory bandwidth, especially when dealing with the large DAG dataset.
Innovation Solution
An information processing device with multiple hash computation circuits and an interconnect system that coordinates bank access, ensuring each circuit specifies different memory banks in the same cycle, thereby avoiding conflicts and maximizing memory bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple hash computation circuits access memory banks sequentially, then the system can be implemented with simple control logic, but bank access conflicts occur and memory bandwidth is not fully utilized
Solution Approach 1:
The memory system is divided into multiple independent banks, and each hash computation circuit is assigned to access a specific bank or set of banks. This segmentation allows parallel access operations without conflicts, as each bank can be accessed independently simultaneously by different circuits.
Solution Approach 2:
The patent implements dynamic bank assignment where hash computation circuits can be flexibly mapped to different memory banks based on current computational needs. The control logic dynamically routes read requests to appropriate banks, enabling adaptive parallel access patterns that maximize bandwidth utilization while avoiding conflicts.
2Productivity
If hash computation circuits access the same memory bank simultaneously, then circuit configuration is simplified, but bank access conflicts occur reducing access efficiency
Solution Approach 1:
The patent introduces a bank dimension to the memory access architecture. Instead of having all circuits compete for the same resource, the system adds the bank number as an additional dimension, allowing multiple circuits to access different banks simultaneously. This transforms a one-dimensional access conflict into a multi-dimensional parallel access system.
Solution Approach 2:
The control logic acts as an intermediary that receives read requests from multiple hash computation circuits and routes them to appropriate memory banks. This intermediary coordinates access patterns, ensuring that simultaneous requests are directed to different banks when possible, thereby preventing conflicts while maintaining high data reading speed.
3Productivity
If sequential access to memory banks is used, then control logic is simpler, but memory latency is not effectively shielded
Solution Approach 1:
The patent enables continuous useful action by allowing multiple hash computation circuits to access memory banks in parallel without waiting for previous accesses to complete. While one circuit accesses Bank 0, another simultaneously accesses Bank 1, and so on. This continuous parallel operation shields memory latency by ensuring that memory access time is overlapped with computation time across multiple circuits.
Data Source
AI summary
To achieve efficient reading of data from a memory including a plurality of banks by specifying different banks and accessing the memory from a plurality of hash computation circuits simultaneously, an information processing device includes a memory 1 including a plurality of banks, a plurality of hash computation circuits 8, and an interconnect 2 respectively connecting the banks in the memory 1 and the hash computation circuits 8 to each other, wherein the hash computation circuits 8 execute control in such a manner that read requests for reading data from the memory 1 respectively include bank numbers for specifying different banks in the same cycle.