Pipelined Hash Circuit with Multi-Frequency Extension Registers
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Solution Overview
Problem
Existing circuits for implementing hash algorithms, such as SHA-256 used in Bitcoin mining, face challenges in optimizing the arrangement and operation of registers in their pipeline structure, leading to high power consumption due to unnecessary register flips, which increases the power consumption computing power ratio.
Innovation Solution
The proposed solution involves a circuit with a pipeline structure where cache registers operate at a first frequency and extension registers are divided into two sets, one operating at the first frequency and the other at a second frequency that is 1/N times the first frequency, allowing for reduced power consumption by eliminating redundant register flips in registers used only for data shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If all registers in the pipeline structure operate at the same high frequency to maintain computing speed, then computing power is preserved, but power consumption increases due to redundant register flips
Solution Approach 1:
The patent segments the extension registers into two distinct sets: first extension registers operating at the first frequency and second extension registers operating at the second frequency (1/N times the first frequency). This segmentation allows different parts of the register system to operate at different frequencies based on their functional requirements, thereby reducing overall power consumption while maintaining computing power for critical operations.
Solution Approach 2:
The patent applies local quality by assigning different operating frequencies to different sets of registers based on their specific functional needs. The first extension registers that participate in logic operations operate at the higher first frequency to maintain computing power, while the second extension registers used only for data shift operations operate at the lower second frequency to reduce power consumption, thus optimizing the local characteristics of each register set.
2Speed
If extension registers operate at the same frequency as cache registers, then data processing speed is maintained, but unnecessary power is consumed by registers only used for data shift
Solution Approach 1:
The patent implements dynamics by making the operating frequency of extension registers adaptable to their functional requirements. The second extension registers used solely for data shift operations dynamically operate at a lower frequency (1/N times the first frequency), while the first extension registers involved in logic operations maintain the higher first frequency, thereby optimizing the balance between data processing speed and energy loss.
Solution Approach 2:
The patent applies periodic action through the use of different clock frequencies for different register sets. The second extension registers operate at a lower frequency that is 1/N times the first frequency, creating a periodic action pattern that matches their data shift function requirements, thereby reducing energy loss while maintaining adequate data processing speed.
Data Source
AI summary
Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.