Hash Compression Accelerator With Parallel Match Path Ordering
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Solution Overview
Problem
Current hash-based compression methods in software are outperformed by dedicated hardware, necessitating acceleration techniques for hash-based compression in microprocessors to improve performance.
Innovation Solution
A method and apparatus for accelerating hash-based compression using a microprocessor's compression accelerator, which involves a Finite-State Machine (FSM) and a hash matcher with multiple hash functions, selectors, and match paths, allowing parallel processing of hash requests and maintaining the original order of compression results through an intermediary buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hash-based compression is implemented in software, then flexibility and ease of implementation are improved, but processing speed and performance deteriorate
Solution Approach 1:
The patent replaces software-based hash computation and string matching with dedicated hardware circuits including hash functions, match paths, matchers, and an intermediary buffer. This hardware substitution achieves both high-speed parallel processing and systematic organization, resolving the contradiction between software flexibility and hardware speed by providing a specialized hardware architecture that maintains implementability while dramatically improving processing performance
2Productivity
If multiple hash requests are processed in parallel, then processing throughput is improved, but maintaining original order of results becomes more difficult
Solution Approach 1:
The patent introduces an intermediary buffer as a mediator between the parallel hash matching circuits and the output. This buffer receives match results from multiple parallel match paths, stores them with their corresponding positions, and then outputs them in the original sequential order. This intermediary component enables parallel processing while automatically maintaining result ordering, resolving the contradiction between throughput improvement and order management complexity
3Productivity
If dedicated hardware is used for hash-based compression, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the hash-based compression function into distinct hardware modules: multiple hash functions for parallel computation, multiple match paths for simultaneous string comparison, matchers for result determination, and an intermediary buffer for order management. This segmentation allows each component to be optimized independently while working together in a coordinated manner, achieving high processing speed through parallelism without creating an unmanageably complex monolithic structure
Data Source
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AI summary
The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.