Hash Computing Core Offsets to Cut Blockchain Communication Overhead
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Solution Overview
Problem
Existing computing units in blockchain technologies face inefficiencies in computation and high costs, necessitating improvements in computation efficiency and cost reduction.
Innovation Solution
A method and apparatus that utilize an N-bit computation offset to enhance computation efficiency by reducing the need for individual computation range allocation information and minimizing register resource usage, achieved by broadcasting computation task data to all computing cores, which perform hash computations based on stored N-bit offsets, and only sending results below a target value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual computation range allocation information is sent to each computing core, then computation accuracy is maintained, but communication overhead and computation time increase
Solution Approach 1:
The patent merges the computation ranges of multiple computing cores into a single unified random number space. Instead of each core maintaining its own separate range allocation information, all cores share a common space with M random numbers, where M is the total number of cores. This eliminates the need for individual range allocation communication while maintaining computation accuracy through the use of computation offsets.
Solution Approach 2:
The patent extracts the essential identifying information (computation offset) from the full range allocation information. Each computing core is assigned a unique N-bit computation offset that serves as a compact identifier within the unified random number space, rather than transmitting complete range allocation data. This extraction reduces communication overhead while preserving the ability to accurately identify and process each core's computation results.
2Reliability
If full random number space is allocated to each computing core, then computation independence is ensured, but register resource usage and chip area increase
Solution Approach 1:
The patent segments the identification of computing cores into two parts: a shared unified random number space containing M random numbers, and individual N-bit computation offsets stored in registers. This segmentation allows the system to maintain computation independence through the combination of the shared space and individual offsets, while using minimal register resources (only N bits per core instead of full range allocation data).
Solution Approach 2:
The unified random number space serves multiple functions simultaneously: it provides the computation range for all cores, enables identification of valid results through the target value comparison, and supports the individual computation offsets. This multi-functional design eliminates the need for separate range allocation structures for each core, reducing chip area while maintaining computation independence.
3Manufacturing precision
If computation range allocation information is transmitted to each computing core, then correct computation boundaries are established, but device complexity and cost increase
Solution Approach 1:
The patent changes the parameter representation from full range allocation information to compact N-bit computation offsets. By representing each core's identity with only N bits (where 2^N >= M), the system maintains accurate computation boundaries while dramatically reducing the complexity of information transmission and storage. The computation boundary accuracy is preserved through the mathematical relationship between the offset and the unified random number space.
Data Source
AI summary
A computation quantity corresponding to each of computing cores is calculated and an initial random number in an N-bit floating-point number form is calculated. The initial random number serves as an N-bit computation offset. Same computation task data is broadcast to all chips of a computing unit. Each of computing cores of each of the chips replaces most-significant N bits of data within the random number space with the N-bit computation offset from a register of the computing core as a starting computation value. M random numbers starting sequentially from the starting computation value within the random number space are used as M candidate computation values. Each of the candidate computation values is combined with the computation task data and a hash computation is performed thereon, and a candidate computation value corresponding to a computation result that is less than a target value is sent to the control unit.