Hash Computing Core Offsets for Low-Overhead Blockchain Processing
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Solution Overview
Problem
Existing computing units in blockchain technologies face inefficiencies in computation and high costs, necessitating improvements in computation efficiency and cost reduction.
Innovation Solution
A method and apparatus that utilize an N-bit computation offset to enhance computation efficiency by reducing the need for individual computation range allocation and minimizing register resource usage, achieved by using a control unit to distribute N-bit computation offsets to computing cores within chips, which perform hash computations based on these offsets and send results to a control unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual computation range allocation is performed for each computing core, then computation precision is improved, but device complexity and data transmission overhead increase
Solution Approach 1:
The patent merges the computation range allocation for all computing cores into a single N-bit computation offset value that is broadcast to all cores simultaneously. Instead of individually allocating computation ranges to each core, the system uses one unified offset that all cores apply to their respective hash computations, thereby reducing data transmission complexity while maintaining computation precision.
Solution Approach 2:
The N-bit computation offset serves multiple functions: it acts as a computation range allocation for all cores, serves as an initial value for hash computations, and enables parallel processing across different chips. This universal offset value replaces multiple individual allocation mechanisms, simplifying the system while preserving computational accuracy.
2Reliability
If full random number space is allocated to each computing core, then computation reliability is improved, but chip area and costs increase
Solution Approach 1:
The patent segments the full random number space into N-bit computation offsets that are distributed across multiple computing cores. Instead of allocating the entire random number space to each core, the system divides it into smaller segments (N bits) that are assigned to individual cores, reducing the memory requirements per core while maintaining overall computation reliability through the collective coverage across all cores.
Solution Approach 2:
The patent transitions from a single-dimension approach (full random number space per core) to a multi-dimensional approach where the random number space is distributed across multiple cores in parallel. The N-bit offset operates in a reduced dimensional space at each core, but the collective computation across all cores achieves the same reliability as the full space would provide individually.
3Adaptability or versatility
If computation targets are adjusted frequently, then adaptability is improved, but data transmission overhead increases
Solution Approach 1:
The patent performs preliminary action by pre-calculating and broadcasting the N-bit computation offset to all computing cores before the actual computation begins. This preliminary allocation allows the computation targets to be adjusted efficiently by simply updating the offset value, which all cores can apply immediately without requiring individual reconfiguration, thereby enabling frequent target adjustments with minimal transmission overhead.
Solution Approach 2:
The patent uses parameter changes by modifying the N-bit computation offset value to adjust computation targets. Instead of changing complex computation parameters individually for each core, the system simply changes this single N-bit parameter that is broadcast to all cores, enabling rapid and efficient adaptation of computation targets with minimal data transmission.
Data Source
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AI summary
Disclosed are a method and apparatus for processing data. A computation quantity corresponding to each of computing cores is calculated based on a random number space and a total number, and an initial random number in an N-bit floating-point number form is calculated based on the computation quantity, wherein the initial random number serves as an N-bit computation offset. Corresponding N-bit computation offsets are sent to chips. Same computation task data is broadcast to all chips of a computing unit, wherein subsequent to receiving the computation task data, each of computing cores of each of the chips replaces most-significant N bits of data within the random number space with the N-bit computation offset from a register of the computing core as a starting computation value, M random numbers starting sequentially from the starting computation value within the random number space are used as M candidate computation values, each of the candidate computation values is combined with the computation task data and a hash computation is performed thereon, and a candidate computation value corresponding to a computation result that is less than a target value is sent to the control unit.