Hash Compute Core for Faster Signature Verification Startup
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Solution Overview
Problem
Conventional hash-based signature verification in processor-based devices is computationally expensive, negatively affecting system startup performance due to the significant number of hash computations required.
Innovation Solution
Implement a hash compute core circuit configured to generate hash chains efficiently by performing a series of operations for a calculated integer value, minimizing data transfer and overhead, and utilizing a ping-pong buffer for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hash-based signature verification is performed using conventional methods, then security and cryptographic validity are ensured, but system startup performance deteriorates due to computationally expensive hash computations
Solution Approach 1:
The patent segments the signature verification process into distinct functional units: a hash compute core circuit for performing hash operations, a ping-pong buffer for parallel data management, and control logic for coordinating operations. This segmentation allows each component to be optimized independently, with the hash compute core dedicated solely to cryptographic computations, thereby improving overall verification speed without compromising security
Solution Approach 2:
The patent introduces a specialized hash compute core circuit as an intermediary component between the main processor and the signature verification algorithm. This dedicated hardware circuit acts as a mediator that offloads computationally intensive hash operations from the general-purpose processor, enabling parallel execution and significantly reducing the time required for signature verification during system startup
2Productivity
If the number of hash computations is reduced to improve startup performance, then system startup performance improves, but signature verification reliability deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-computing and storing hash chain values in a ping-pong buffer structure before they are needed for verification. The buffer is organized to allow parallel access to pre-computed values, eliminating the need to perform all hash computations sequentially during startup. This approach maintains the full computational integrity required for secure verification while dramatically reducing the time needed to complete the process
3Loss of time
If a dedicated hash compute core circuit is implemented, then computation time is reduced, but device complexity increases
Solution Approach 1:
The hash compute core circuit is designed with universal functionality that can execute multiple hash algorithms (such as SHA-256, SHA-3, and other cryptographic hash functions) through a single unified hardware structure. The circuit accepts algorithm-specific parameters and configuration inputs, allowing it to adapt to different hash function requirements without requiring separate dedicated circuits for each algorithm. This multi-functionality reduces overall device complexity while maintaining fast verification performance across various cryptographic standards
Data Source
AI summary
Enabling efficient hash-based signature verification in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device includes a processor device and a hash compute core circuit. The hash compute core circuit receives, from a process executing on the processor device, a digit of a plurality of digits of a message digest, a signature value corresponding to the digit, and an initialized context value. The hash compute core circuit generates a hash chain by being configured to, for Y times wherein Y is an integer value calculated using a value of the digit, update the context value, and perform a hash operation on the signature value. The hash compute core circuit then transmits an ending value of the hash chain to the process, which stores the ending value of the hash chain.