SHA-256 Hash Engine Clock Tree for Hold Time and Frequency
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Solution Overview
Problem
Current Bitcoin mining devices face challenges in achieving a low power-consumption-to-hash-rate ratio, which is crucial for efficient cryptocurrency mining, due to limitations in clock signal distribution and register timing requirements in SHA-256 algorithm implementation.
Innovation Solution
A novel clock tree solution is introduced, employing a combination of forward and reverse clock tree structures within a pipeline architecture, where specific register classifications utilize either forward or reverse clock trees to meet hold time requirements while maximizing chip frequency, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional clock tree structure is used in SHA-256 hash engine, then the circuit structure is simple, but the chip running frequency is limited and hold time requirements cannot be met
Solution Approach 1:
The clock tree is segmented into forward clock trees and reverse clock trees, with different register groups (first group and second group) receiving clock signals from different directions. This segmentation allows each segment to be optimized independently, enabling the chip to achieve higher running frequency while meeting hold time requirements through the reverse clock tree structure.
Solution Approach 2:
The patent introduces a reverse clock tree structure where the second group of registers receives clock signals in the opposite direction to the data flow. This inversion of the conventional clock distribution approach allows the clock signal to arrive at registers after the data signal, thereby satisfying the hold time requirement and enabling higher operating frequencies.
2Reliability
If clock signal delivery direction is opposite to digital signal delivery direction, then hold time requirement is met, but clock tree structure becomes complex
Solution Approach 1:
The register file is divided into two groups: first group registers receive clock signals in the same direction as data flow, while second group registers receive clock signals in the opposite direction. This segmentation allows the system to meet hold time requirements for critical paths without making the entire clock tree complex, as only specific register groups use the reverse clock tree approach.
Solution Approach 2:
Different parts of the register file have different clocking requirements. The patent applies reverse clock tree structure locally to the second group of registers that require strict hold time satisfaction, while the first group uses conventional forward clock trees. This localized application of reverse clocking minimizes overall structural complexity while meeting reliability requirements where needed.
Data Source
AI summary
This disclosure relates to a device performing hash algorithm. A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation stage. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.