Cryptographic Hash Instruction with Multi-Iteration Processing
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Solution Overview
Problem
Existing cryptographic hash algorithms, particularly SHA-1, are limited by the need to perform each iteration sequentially, which exceeds the timing requirements of modern processors, leading to suboptimal performance in processing workloads.
Innovation Solution
Implementing a cryptographic hash instruction that allows for at least two iterations of the cryptographic hash function to be performed per processing cycle, utilizing unrolled multi-iteration logic circuitry or pipeline stages to parallelize computations and meet timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If only one iteration of cryptographic hash function is performed per processing cycle, then timing requirements are met and implementation is simpler, but processing performance is limited and total execution time increases
Solution Approach 1:
The cryptographic hash function iterations are segmented into multiple parallel processing paths within a single processing cycle. The processing circuitry is divided into multiple functional units that can simultaneously execute different iterations, with each unit handling a specific iteration while sharing common resources through time-multiplexed access.
Solution Approach 2:
Operand preparation and routing are performed in advance within the processing cycle before the actual hash function computations begin. Input operands are pre-loaded into different processing units, and control signals are pre-configured to enable seamless switching between iterations without interrupting the main computation flow.
2Loss of time
If multiple iterations of cryptographic hash function are performed per processing cycle, then total execution time is reduced, but timing requirements become more difficult to meet
Solution Approach 1:
The processing circuitry maintains continuous computational activity across multiple iterations within a single processing cycle by eliminating idle periods. Each processing unit continuously performs hash function operations on different iterations, and resource sharing is designed to avoid any interruption in the computational flow, ensuring that every clock cycle is productively utilized.
Solution Approach 2:
Multiple iteration computations are merged into a single processing cycle by combining the functional units and sharing common resources such as arithmetic logic units, registers, and control logic. The merging is achieved through careful resource allocation and time-multiplexed access patterns that allow different iterations to share the same hardware resources without conflict.
3Productivity
If multiple iterations are performed per processing cycle, then processing efficiency is improved, but the complexity of meeting timing constraints increases
Solution Approach 1:
The control logic incorporates feedback mechanisms that monitor the completion status of each iteration and dynamically adjust the timing of resource allocation. Completion flags from each processing unit feed back to the control logic, which then coordinates the switching of shared resources to ensure that timing constraints are met while maximizing processing efficiency.
Data Source
AI summary
An apparatus comprises instruction decoding circuitry to decode a cryptographic hash instruction specifying at least one working operand and an input operand; and processing circuitry to perform, in response to decoding of the cryptographic hash instruction, two or more iterations of a cryptographic hash function. Each iteration of the cryptographic hash function comprises determining an updated value for the at least one working operand based on a previous value for the at least one working operand and a respective portion of the input operand selected to be processed in that iteration. The updated value for the at least one working operand in one iteration becoming the previous value for the at least one working operand in a next iteration. In response to decoding of the cryptographic hash instruction, the processing circuitry performs at least two iterations of the cryptographic hash function per processing cycle.