Internal State Tracking via Hash Observation Bus in IC Testing
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Solution Overview
Problem
Existing testing tools and techniques for integrated circuits, such as processors, struggle to capture a satisfactory percentage of errors and provide adequate coverage of various circuits and functionalities, particularly in units like fetch/branch prediction circuitry, due to internal states being invisible to software.
Innovation Solution
Implementing a hash value calculation circuit coupled to hardware functional units via an observation bus, allowing these units to autonomously and unilaterally communicate data elements for calculating hash values, which are then compared to expected values to detect errors, with standardized interfaces that remain static throughout development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If random instruction sequence (RIS) tools and techniques are used to test processors, then testing can be performed, but error detection coverage and circuit functionality coverage remain insufficient
Solution Approach 1:
The patent introduces an intermediary hashing mechanism that aggregates internal state data from multiple hardware functional units into compressed hash values. This mediator layer enables comprehensive error detection coverage without requiring direct access to all internal states, thus maintaining testing effectiveness while reducing system complexity.
Solution Approach 2:
The patent transforms the testing approach by changing parameters from direct internal state observation to hash value comparison. By computing hash values of internal states and comparing them against expected hash values, the system achieves higher error detection coverage with simpler testing infrastructure.
2Measurement precision
If internal states of hardware functional units are made observable for testing, then error detection improves, but interface complexity and testbench requirements increase
Solution Approach 1:
The patent extracts only the essential information needed for testing by computing hash values of internal states rather than exposing all internal state data. This extraction approach provides sufficient measurement precision for error detection while minimizing interface and testbench complexity.
Solution Approach 2:
The patent creates simplified copies of internal state information in the form of hash values. These hash value copies serve as proxies for the actual internal states, enabling observability without requiring complex interfaces or testbenches to access the original detailed states.
3Productivity
If standardized static interfaces are implemented for hash value calculation, then flexibility and efficiency improve, but adaptability to different hardware functional units may be limited
Solution Approach 1:
The patent implements universal hashing interfaces that can work with multiple types of hardware functional units. The hash value calculation mechanism is designed to be hardware-agnostic, accepting data elements from various functional units (ALU, FPU, branch prediction, etc.) through standardized interfaces, thus achieving both efficiency and adaptability.
Data Source
AI summary
The present disclosure relates generally to integrated circuits and relates more particularly to circuits, systems, and/or processes for common control and/or observation for internal state tracking.