Hash-Based System Address Map for Multi-Chip Node Routing
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Solution Overview
Problem
Existing System Address Maps (SAM) struggle to efficiently identify target nodes in multi-chip data processing systems, especially when memory is fine-grained and interleaved across chips, as they lack sufficient registers to program all possible memory regions, making it impractical to compare address ranges and identify target nodes accurately.
Innovation Solution
The System Address Map logic is modified to include a node register table that stores identifiers for both local and remote connection nodes, using hash address logic to generate a pointer for the node register table and a multiplexer to output the correct node identifier, enabling access to both on-chip and off-chip data resources by distinguishing between local and remote memory addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional System Address Map with limited registers is used, then the device complexity is reduced, but it cannot accurately identify target nodes in fine-grained interleaved memory configurations across multiple chips
Solution Approach 1:
The System Address Map is segmented into multiple specialized components: a hash address logic unit that processes address bits to generate indices, a node register table with multiple registers storing node identifiers, and a multiplexer that selects the appropriate identifier. This segmentation allows each component to perform its function efficiently, resolving the contradiction between accuracy and complexity by distributing the identification task across modular units rather than requiring a single complex structure.
Solution Approach 2:
The patent introduces a new dimension of address processing by using hash function logic to transform address bits into indices that access the node register table. This dimensional transformation allows the system to map a large address space onto a manageable set of registers, achieving accurate target node identification without requiring a register for every possible memory region.
2Measurement precision
If sufficient registers are provided to program all memory regions, then target node identification accuracy improves, but the device complexity and resource requirements become impractical
Solution Approach 1:
The patent changes the parameter of address processing by applying hash function logic to transform address bits into compact indices. Instead of directly mapping each memory region to a dedicated register (which would require an impractical number of registers), the hash function compresses the address space into a manageable set of indices that can be stored in a limited number of registers, achieving comprehensive memory region coverage with feasible resource requirements.
Solution Approach 2:
The node register table stores multiple node identifiers in a compact structure where each register can hold identifiers for different chip types (local or remote connection nodes). This copying approach allows the same register structure to serve multiple memory regions by storing replicated identifier patterns, reducing the total number of registers needed while maintaining accurate identification across all memory regions.
3Productivity
If the System Address Map distinguishes between local and remote memory addresses, then routing efficiency to correct target nodes improves, but the address mapping logic becomes more complex
Solution Approach 1:
The hash address logic unit performs preliminary processing of the address bits to generate an index before the actual node identifier selection occurs. This preliminary action classifies the address into categories (local or remote memory) and prepares the appropriate index for accessing the node register table, enabling efficient routing decisions to be made early in the address mapping process without adding significant complexity to the overall logic.
Data Source
AI summary
A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.