Hash Value Calculation Method for FPGA Memory Efficiency
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Solution Overview
Problem
Existing techniques for implementing hash tables on Field Programmable Gate Arrays (FPGAs) face challenges in achieving high memory space efficiency due to the need for multiple hash functions and the inability to complete hash-value calculations within one clock cycle, particularly with the universal hashing framework, which requires multiplication and remainder calculations that digital signal processors cannot perform quickly enough.
Innovation Solution
A method for calculating hash values by selecting and assigning bits in a predetermined position, allowing for the generation of a hash function family that can output different hash values for continuous keys, ensuring all memory slots are filled and optimizing memory usage, while completing calculations within one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If universal hashing framework is used to generate multiple hash functions, then hash table space efficiency is improved, but calculation speed deteriorates due to multiplication and remainder operations requiring multiple clock cycles
Solution Approach 1:
The patent changes the calculation parameters from multiplication and remainder operations to bit selection and XOR operations. By selecting specific bits from the input key at predetermined positions and XORing them to generate hash values, the calculation can be completed within one clock cycle while still achieving uniform distribution across memory slots
Solution Approach 2:
The patent substitutes complex arithmetic operations (multiplication and remainder) with simpler logical operations (bit selection and XOR). This replacement maintains the hash function's ability to distribute keys uniformly while dramatically reducing the computational time required
2Quantity of substance
If multiple hash functions are implemented on FPGA, then memory space efficiency is improved, but device complexity increases due to need for multiple calculation circuits
Solution Approach 1:
The patent creates a universal hash function generation mechanism where a single circuit design can generate multiple different hash functions by varying the bit selection positions. This multi-functional approach allows one circuit to perform the work of multiple dedicated circuits, reducing overall device complexity while maintaining the ability to fill all memory slots
Solution Approach 2:
The patent introduces dynamic bit selection where the positions of selected bits can be changed to generate different hash functions. This dynamic approach allows a single static circuit to produce multiple hash function behaviors, eliminating the need for multiple fixed circuits
3Productivity
If hash table is optimized for specific key characteristics, then retrieval efficiency is improved, but adaptability deteriorates when key characteristics are unknown or change
Solution Approach 1:
The patent performs preliminary bit selection setup where the positions for bit selection are predetermined based on the desired hash function characteristics. This preliminary configuration allows the system to achieve optimal retrieval efficiency for various key types without needing to know the specific key characteristics in advance, as the bit selection scheme is designed to work effectively across different key distributions
Data Source
AI summary
The present invention provides a method of calculating a hash value, the method making it possible to generate one or more hash functions by changing a predetermined position for selecting a bit, the length of an input key being L bits, the length of a hash value being N bits, and N≤L, the method including a computer performing calculation of a generated certain one hash function by selecting one bit present in a certain predetermined position among lower N bits of the input key, assigning the selected one bit to a bit in a certain predetermined position among N bits of the hash value, and repeating the selecting and the assigning a bit not selected yet in the selecting among the lower N bits of the key to the hash value until all bits not assigned yet of the hash value are assigned.