Hash Value Generating Device Parallel Processing Optimization

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Solution Overview

Problem

The KECCAK algorithm for generating hash values faces challenges in throughput due to the need to store and process large amounts of data in memory during its round processing steps, particularly in steps θ, π, and χ, which limits speed and efficiency.

Innovation Solution

The proposed solution involves optimizing the processing by performing steps in units of planes or sheets instead of lanes, allowing for pipelined processing and reducing the need for holding state data pieces, thereby improving throughput by enabling parallel operation of processing circuits and reducing the time required for one-time round processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If round processing is performed by storing results in memory for θ and π steps, then data processing completeness is improved, but processing speed deteriorates due to repeated memory access

Engineering Contradiction:
Improvedata processing completenessVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The round processing is divided into two independent processing circuits: a first processing circuit for θ, ρ, and π steps, and a second processing circuit for χ and ι steps. This segmentation allows parallel execution of different processing stages, eliminating the sequential memory access bottleneck while maintaining complete data processing through dedicated functional units in each circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first processing circuit performs θ, ρ, and π processing in advance to generate intermediate results that are then fed to the second processing circuit. By preparing data beforehand in the first circuit, the second circuit can operate continuously without waiting for memory access, thus improving overall processing speed while ensuring data completeness.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If all round processing steps are performed sequentially in one circuit, then device complexity is reduced, but throughput deteriorates due to inability to parallelize processing

Engineering Contradiction:
Improvecircuit structure simplicityVSAvoidthroughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The processing circuit is segmented into two independent circuits handling different steps of the round function. The first circuit handles θ, ρ, and π steps while the second circuit handles χ and ι steps. This segmentation enables parallel processing of multiple operations simultaneously, dramatically improving throughput without requiring an overly complex single-circuit design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple processing steps (θ, ρ, π in the first circuit and χ, ι in the second circuit) are merged into parallel operational flows. By combining these steps into two synchronized processing circuits that operate simultaneously, the system achieves high throughput while maintaining manageable complexity through modular architecture.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If processing is performed in units of lanes, then memory storage requirements are reduced, but processing time increases due to sequential handling of state data

Engineering Contradiction:
Improvememory storage requirementsVSAvoidprocessing time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The processing approach transitions from sequential lane-by-lane handling to parallel plane-based processing. By organizing data into planes and using multiple processing circuits that operate on different planes simultaneously, the system reduces the time required to process state data while maintaining efficient memory utilization through the plane-oriented data flow.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP2965305B1Hash value generating device
Publication Date: 2020.10.28 CANON KK
  • EP2965305B1 patent drawingFigure 1A~1C
  • EP2965305B1 patent drawingFigure 2A~2C
  • EP2965305B1 patent drawingFigure 2D~2F

AI summary

A hash value generating device for generating a hash value based on the KECCAK algorithm includes a θ processing unit, a ρ processing unit, a п processing unit, a χ processing unit, and an ɩ processing unit for performing processing of five steps θ, ρ, п, χ, and ɩ, included in round processing of the KECCAK algorithm. The п processing unit receives input of data in units of planes and outputs data in units of sheets.