Multi-Scheme Hash Verification Circuit Sharing
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Solution Overview
Problem
Existing digital signature verification systems face inefficiencies due to the need for separate cryptographic hash circuits and memory resources for different hash-based digital signature verification schemes, leading to increased circuit size, power consumption, and manufacturing costs.
Innovation Solution
A multi-scheme hash-based digital signature verification system that utilizes a shared cryptographic hash circuit and memory for both LMS and XMSS schemes, allowing sequential or alternating verification to reduce circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate cryptographic hash circuits are used for different hash-based digital signature verification schemes, then verification capability for multiple schemes is maintained, but circuit size increases
Solution Approach 1:
The patent implements a universal cryptographic hash circuit that can operate with multiple hash functions (SHA-256, SHA-512, BLAKE2, etc.) through configurable parameters and selection logic. This single multi-functional circuit replaces what would otherwise require multiple separate dedicated circuits, thereby reducing overall circuit area while maintaining the ability to verify digital signatures across different hash-based schemes.
Solution Approach 2:
The patent merges the cryptographic hash circuit functionality for different hash-based digital signature verification schemes into a single shared circuit. By combining the hash computation capabilities and sharing common resources (such as logic gates, lookup tables, and control units), the design achieves compact implementation while supporting multiple verification schemes simultaneously or sequentially.
2Reliability
If separate memory resources are allocated for different hash-based digital signature verification schemes, then scheme-specific data storage is ensured, but device complexity increases
Solution Approach 1:
The patent employs a universal memory structure that can be configured to store data for different hash-based digital signature verification schemes. Through programmable address mapping and configurable data organization, the same memory resource serves multiple schemes, eliminating the need for separate dedicated memory blocks and reducing overall device complexity while ensuring reliable storage for each scheme's specific requirements.
Solution Approach 2:
The patent implements dynamic memory allocation and configuration where memory resources can be flexibly assigned to different verification schemes based on operational needs. The system can dynamically reconfigure memory addressing, data width, and access patterns to accommodate different schemes, providing scheme-specific storage guarantees without requiring static separate memory allocations, thus reducing device complexity.
3Speed
If multiple dedicated cryptographic hash circuits are implemented, then verification speed for each scheme is optimized, but power consumption increases
Solution Approach 1:
The patent implements periodic or alternating operation of the shared cryptographic hash circuit for different verification schemes. Instead of maintaining multiple circuits in parallel, the system switches between supporting different schemes in time-multiplexed fashion, with each scheme receiving dedicated processing periods. This approach maintains verification speed performance while significantly reducing power consumption by keeping only one circuit active at a time.
Solution Approach 2:
The patent combines multiple cryptographic hash circuit functionalities into a single shared circuit that can be dynamically configured. By merging the circuits and using resource sharing with proper timing and control, the system achieves verification speeds comparable to dedicated circuits while reducing power consumption proportional to the number of circuits merged, since only one instance operates actively at any given moment.
Data Source
AI summary
A digital signature verification unit or other apparatus of an aspect includes cryptographic hash circuitry to generate cryptographic hashes and multi-scheme hash-based digital signature verification circuitry coupled with the cryptographic hash circuitry. The multi-scheme hash-based digital signature verification circuitry is to use the cryptographic hash circuitry to verify digital signatures according to only one of a plurality of hash-based digital signature verification schemes at a time, the plurality of hash-based digital signature verification schemes including a first hash-based digital signature verification scheme and a second hash-based digital signature verification scheme. Other apparatus, methods, and systems are disclosed.