Dynamic Hash Verification Control Register for ROP Attack Protection
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Solution Overview
Problem
Modern computing systems face challenges in securely managing access to information handling and data processing systems, particularly in preventing unauthorized access through techniques like Return Oriented Programming (ROP) and Data Oriented Programming (DOP) attacks, which can lead to performance overhead due to the need for cryptographic hash verification mechanisms.
Innovation Solution
A processor-based system that operates in either secure or performance modes, using a single instruction to compute and store a cryptographic hash value in secure mode, and treating it as a no-operation in performance mode, with dynamic control via a control register to switch between modes without additional overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic hash verification mechanisms are implemented to protect against ROP and DOP attacks, then security is improved, but processor performance deteriorates due to the overhead of computing and verifying hash values at each function call
Solution Approach 1:
The patent implements dynamic control of hash verification through a control register that can be set by the operating system to enable or disable the feature at runtime. This allows the system to adapt between security-critical modes (where hash verification is enabled) and performance-critical modes (where it is disabled), resolving the contradiction by making the security mechanism dynamic rather than static.
Solution Approach 2:
The patent changes the operational parameter of the hash verification mechanism through a control register bit. When the bit is set, the processor computes and verifies hash values; when cleared, it executes no-operations. This parameter change allows the same hardware to operate in two distinct states, balancing security and performance based on system needs.
2Reliability
If hash verification instructions are executed at every function call to ensure security, then protection against malicious attacks is improved, but execution time increases due to the additional computational overhead
Solution Approach 1:
The control register enables dynamic switching between security and performance modes. In performance mode, the hash verification instructions are transformed into no-operations, eliminating execution time overhead while maintaining the instructional structure. This dynamic adaptation resolves the time-security contradiction.
Solution Approach 2:
When in performance mode, the patent uses inexpensive no-operation instructions instead of costly hash computation instructions. These no-ops are computationally trivial and consume minimal time, effectively replacing the expensive security verification with a cheap placeholder that maintains code structure without the performance penalty.
3Reliability
If security mode is enabled to compute and verify hash values, then system security is improved, but device complexity increases due to the additional control register and mode switching mechanisms
Solution Approach 1:
The control register serves multiple functions: it acts as a security enable/disable switch, a performance optimization control, and a runtime configuration mechanism. By making this single register multi-functional, the patent reduces the need for separate control structures, thereby managing complexity while providing comprehensive control over the hash verification feature.
Data Source
AI summary
A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.