Hashed Fetch Address Prediction for Shorter Instruction Pipelines

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Solution Overview

Problem

The lengthy instruction fetch process in processors is caused by sequential access to memory structures and long pipeline stages, leading to increased latency and idle execution units due to branch mispredictions.

Innovation Solution

A prediction unit with first and second predictors that provide hashed fetch addresses to parallelize the instruction fetch pipeline, using branch target buffer predictions to access the instruction cache in a folded mode, reducing the number of stages required for instruction fetch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential access to memory structures is used in the instruction fetch process, then the instruction cache can be accessed systematically, but the pipeline length increases and latency is increased

Engineering Contradiction:

Improveinstruction fetch accuracyVSAvoidinstruction fetch latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by using branch target buffer predictions to pre-determine the next fetch address before the instruction fetch process completes. This allows the system to prepare the next memory access address in advance, reducing the effective latency of the instruction fetch pipeline while maintaining systematic cache access patterns.

Inventive Principle:

Principle #10Preliminary action

2Speed

If a long instruction fetch pipeline is implemented to handle address translation and cache access, then high processor clock frequency is achieved, but branch misprediction latency increases and execution units idle longer

Engineering Contradiction:

Improveprocessor clock frequencyVSAvoidbranch misprediction penalty

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent implements feedback by continuously monitoring branch outcomes and updating branch target buffer entries based on actual execution results. This feedback mechanism allows the system to learn from mispredictions and improve future predictions, reducing the frequency and impact of branch misprediction penalties while maintaining high clock frequency operation.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The branch target buffer performs preliminary action by predicting and storing target addresses of branch instructions before they are executed. This allows the instruction fetch unit to speculatively fetch instructions from predicted target addresses in advance, reducing the effective misprediction penalty when branches are taken, while the processor continues to operate at high clock frequency.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If multiple ways of instruction cache are read out to handle aliasing, then hit rate is improved, but power consumption increases

Engineering Contradiction:

Improvecache hit rateVSAvoidinstruction cache power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by using hashed fetch addresses to selectively access only the specific way in the instruction cache that is likely to contain the required instruction block. Instead of reading out all ways in the cache set, the system performs a targeted access based on hash computation, achieving sufficient cache hit rate while significantly reducing power consumption compared to reading all ways.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12487830B1Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Publication Date: 2025.12.02 VENTANA MICRO SYSTEMS INC

AI summary

A prediction unit includes a first predictor that provides an output comprising a hashed fetch address of a current fetch block in response to an input. The first predictor input comprises a hashed fetch address of a previous fetch block that immediately precedes the current fetch block in program execution order. A second predictor provides an output comprising a fetch address of a next fetch block that immediately succeeds the current fetch block in program execution order in response to an input. The second predictor input comprises the hashed fetch address of the current fetch block output by the first predictor.