Hashed Multi-Bank TLB Layout for Contiguous Page Translation
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Solution Overview
Problem
Existing translation lookaside buffer (TLB) implementations using standard RAMs face inefficiencies in managing contiguous and non-contiguous translation entries, leading to issues such as space wastage, bandwidth limitations, and latency problems due to fluctuating ratios and mismatched memory usage.
Innovation Solution
A TLB circuit design that computes mathematically uncorrelated hash values to concurrently locate contiguous and non-contiguous translation entries in separate TLB banks, allowing simultaneous allocation and comparison, thereby optimizing memory usage and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard RAM is used to implement TLB, then implementation simplicity is improved, but space utilization efficiency deteriorates due to fluctuating ratios of contiguous and non-contiguous entries
Solution Approach 1:
The patent divides the TLB into separate banks: contiguous TLB banks dedicated to storing contiguous translation entries and non-contiguous TLB banks dedicated to storing non-contiguous translation entries. This segmentation allows each bank to be optimized for its specific entry type, improving space utilization efficiency by eliminating the waste that occurs when a single RAM must accommodate both entry types with fluctuating ratios.
2Device complexity
If single TLB bank is used, then device complexity is reduced, but access latency increases due to sequential allocation and comparison
Solution Approach 1:
By segmenting the TLB into separate contiguous and non-contiguous banks, the patent enables parallel access operations. The processor can simultaneously access both banks to locate translation entries, reducing access latency compared to sequential access in a single bank, while maintaining manageable complexity through clear functional separation.
Solution Approach 2:
The patent pre-organizes translation entries into dedicated banks based on their type (contiguous or non-contiguous) before access occurs. This preliminary organization eliminates the need for sequential search and allocation during actual translation operations, significantly reducing access latency.
3Device complexity
If contiguous and non-contiguous entries are stored in same TLB bank, then device complexity is minimized, but bandwidth utilization deteriorates due to mismatched memory usage
Solution Approach 1:
The patent segments TLB banks into contiguous-specific and non-contiguous-specific banks, allowing each bank to be optimized for its entry type. This improves bandwidth utilization by ensuring that memory resources are dedicated to specific access patterns, eliminating the mismatched memory usage that occurs when both entry types share the same bank.
Solution Approach 2:
Each TLB bank is given specialized quality characteristics: contiguous banks are optimized for contiguous entry storage and access, while non-contiguous banks are optimized for non-contiguous entries. This local optimization of bank characteristics improves overall bandwidth utilization by matching memory organization to access patterns.
Data Source
AI summary
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.