Hashing Engine Verification Path for Clock-Domain Metastability
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Solution Overview
Problem
Existing hashing engine circuitry experiences metastability issues due to different clock domains between central control logic and hashing engine components, leading to increased power consumption and reduced hashing speed when synchronization circuitry is used.
Innovation Solution
A hashing engine circuitry design that mitigates metastability without synchronization circuitry by using core circuitry to generate hashes directly from unsynchronized input signals and verifier circuitry to verify the results using synchronized signals, allowing for efficient hash generation and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization circuitry is used to mitigate metastability between clock domains, then reliability is improved, but power consumption increases and hashing speed decreases
Solution Approach 1:
The system is divided into two independent processing paths: a first processing circuit that operates on unsynchronized input signals without clock domain synchronization, and a second processing circuit that operates on synchronized signals. This segmentation allows the majority of hashing operations to proceed at full speed while only verification operations use synchronization, thus maintaining high productivity while ensuring reliability.
Solution Approach 2:
The second processing circuit acts as an intermediary verification mechanism. It receives both the unsynchronized input signal and a synchronized version of the same signal, processes both through the same hashing function, and compares results to detect metastability errors. This intermediary approach ensures reliability without requiring all processing to go through the slower synchronized path.
2Reliability
If synchronization circuitry is used to mitigate metastability between clock domains, then reliability is improved, but power consumption increases
Solution Approach 1:
The processing workload is segmented into two paths: a primary path using unsynchronized signals that consumes less power and operates at higher speed, and a verification path using synchronized signals that consumes more power but ensures reliability. This segmentation minimizes overall power consumption by limiting the use of power-intensive synchronization circuitry to only when necessary for verification.
Solution Approach 2:
Instead of applying synchronization to all hashing operations (excessive action), the system applies synchronization only to the verification path (partial action). This partial application of synchronization is sufficient to detect metastability errors while avoiding the excessive power consumption that would result from synchronizing all processing operations.
3Productivity
If unsynchronized input signals are used directly in hashing operations, then hashing speed increases, but metastability errors may occur
Solution Approach 1:
The second processing circuit serves as an intermediary error-detection mechanism. It receives the same unsynchronized input signal that the first processing circuit uses, independently processes it through the hashing function, and compares its output with the first circuit's output. Any discrepancies indicate metastability errors, allowing the system to maintain high-speed processing while detecting reliability issues.
Solution Approach 2:
The system implements feedback through comparison of results from the two processing circuits. When the second processing circuit detects a mismatch between its output and the first processing circuit's output, it generates an error signal indicating a metastability error. This feedback mechanism enables the system to maintain high-speed operation while providing real-time detection of reliability issues.
Data Source
AI summary
An example system, includes clock synchronization circuitry, first data processing circuitry, and second data processing circuitry electrically coupled to the clock synchronization circuitry and the first processing circuitry. The clock synchronization circuitry is configured to receive a first signal, and output a second signal synchronized to a clock domain of the second data processing circuitry. The first data processing circuitry is configured to perform one or more first computations based on the first signal, and provide, to the second data processing circuitry, a result corresponding to the one or more first computations. The second data processing circuitry is configured to perform one or more second computations based on the second signal, determine whether the one or more second computations satisfies a selection criterion, and generate output data representing whether the one or more second computations satisfies the selection criterion.