Hashing Mechanism for Page Table Entry Compression
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Solution Overview
Problem
Virtual memory addressing in computing systems consumes significant resources, particularly when running applications with large memory footprints, leading to increased pressure on the system's cache and memory capacity due to the length of cached address translation entries.
Innovation Solution
A hierarchical page table is traversed using a hashing mechanism to reduce the size of each entry, increasing the per-node fanout and the maximum physical address space, allowing for more efficient virtual-to-physical address translations and improved application performance by reducing latency and memory consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional pointer-based page table entries are used, then address translation functionality is maintained, but entry size remains large (e.g., 64 bits) consuming significant cache and memory resources
Solution Approach 1:
The patent extracts the address translation functionality from the traditional pointer-based page table entry structure. Instead of storing complete physical address pointers in each page table entry, the invention extracts only the necessary translation information and uses a hashing mechanism to compute physical addresses on-demand, thereby reducing the size of cached address translation entries and lowering resource consumption.
Solution Approach 2:
The invention changes the parameter of page table entry size by replacing the traditional pointer-based structure with a hashed address representation. This parameter change reduces the number of bits required per entry (e.g., from 64 bits to fewer bits), directly addressing the resource consumption issue while maintaining address translation functionality through the hash-based retrieval mechanism.
2Quantity of substance
If hashed address representation is used to reduce entry size, then cache and memory resources are reduced, but address translation complexity increases
Solution Approach 1:
The patent replaces the mechanical pointer-chasing mechanism of traditional page table traversal with a hashing-based system. Instead of following pointer chains through multiple levels of page tables, the invention uses hash functions to directly compute and retrieve address translations, substituting the mechanical navigation process with a computational approach that reduces memory access overhead.
3Adaptability or versatility
If pointer-based page table entries are used, then address translation is straightforward, but the reach of translation lookaside buffers is limited
Solution Approach 1:
The invention introduces a new dimension to address translation by using hashed address representation instead of traditional pointer structures. This dimensional change in how addresses are represented and retrieved allows translation lookaside buffers to store more entries within the same resource constraints, effectively doubling the reach of level 2 TLBs by reducing the bits required per entry.
Data Source
AI summary
A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.