HATS Engine for Implicit Address Translation in NVMe
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Solution Overview
Problem
Existing address translation technologies, such as ATS/ATC, are inefficient and costly due to the requirement for a large cache buffer and high-performance lookup operations, leading to increased area, cost, and power consumption.
Innovation Solution
Implementing a Host Interface Module (HIM) address translation search engine (HATS) that monitors pointers with untranslated addresses, fetches translated addresses, and updates the status of pointers, thereby reducing the reliance on ATS/ATC and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a real ATC cache is implemented as defined in PCIe standard, then address translation capability is improved, but device area, cost and power consumption increase significantly
Solution Approach 1:
The patent extracts the ATC functionality from the PCIe layer and implements it at the NVMe layer instead. By taking out the cache mechanism from its traditional PCIe location and relocating it to the NVMe command structure, the system achieves address translation capability while avoiding the need for a separate PCIe ATC hardware block, thereby reducing power consumption and device area.
Solution Approach 2:
The patent merges the ATC functionality with the NVMe command structure. The address translation cache is integrated into the NVMe command processing flow, combining two previously separate functions (PCIe address translation and NVMe command processing) into a unified mechanism, which eliminates the need for dedicated ATC hardware and reduces overall device complexity and power consumption.
2Reliability
If a real ATC cache is implemented as defined in PCIe standard, then address translation capability is improved, but device area and cost increase significantly
Solution Approach 1:
The patent extracts the ATC functionality from the PCIe layer and implements it at the NVMe layer instead. By taking out the cache mechanism from its traditional PCIe location and relocating it to the NVMe command structure, the system achieves address translation capability while avoiding the need for a separate PCIe ATC hardware block, thereby reducing device area.
Solution Approach 2:
The patent merges the ATC functionality with the NVMe command structure. The address translation cache is integrated into the NVMe command processing flow, combining two previously separate functions (PCIe address translation and NVMe command processing) into a unified mechanism, which eliminates the need for dedicated ATC hardware and reduces overall device complexity and area.
3Reliability
If ATS/PRI functionality is implemented with a real cache, then address translation performance is improved, but productivity decreases due to more complex operations
Solution Approach 1:
The patent extracts the ATC functionality from the PCIe layer and implements it at the NVMe layer. This extraction simplifies the processing flow by eliminating the need for complex PCIe ATC hardware operations and integrating address translation directly into the NVMe command processing, thereby improving productivity while maintaining translation performance.
Solution Approach 2:
The patent uses a simplified copy of the ATC mechanism implemented at the NVMe layer rather than a full PCIe ATC implementation. This simplified version achieves the necessary address translation functionality without the complexity and overhead of a complete PCIe ATC system, improving processing efficiency while maintaining sufficient translation performance.
Data Source
AI summary
The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated. After PRI completes, the device will return to using the HATS to get all the translated addresses for the pointers with an untranslated address status. After getting the translated addresses, the device shall use the translated addresses to perform DMA operations.