HBA I/O Virtualization via Single External Memory Interface

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional network and storage architectures in cloud computing face performance and administrative bottlenecks, particularly in handling input/output (I/O) operations, which hinder efficient I/O virtualization across InfiniBand (IB) fabrics.

Innovation Solution

The implementation of a system that supports I/O virtualization using a single memory interface, employing a free buffer pool with a hybrid linked list structure to manage disk read data and context, allowing for efficient handling of ingress traffic and multiple virtual host bus adaptors (vHBAs) without the need for multiple external memories or message passing, thereby reducing latency and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional network and storage architectures are used in cloud computing, then system stability is maintained, but performance bottlenecks occur and I/O virtualization efficiency deteriorates

Engineering Contradiction:
ImproveI/O virtualization efficiencyVSAvoidarchitecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the management of packet buffers for multiple virtual HBAs into a single shared free buffer pool in external memory, eliminating the need for separate buffer pools for each vHBA. This consolidation reduces memory overhead and simplifies the architecture while improving I/O virtualization efficiency through unified buffer management.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The free buffer pool is designed as a universal memory structure that serves multiple virtual HBAs simultaneously. The hybrid linked list structure enables the same memory resources to be dynamically allocated to different vHBAs based on demand, providing multi-functional buffer management that improves productivity without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple external memories are used to manage disk read data for multiple vHBAs, then data access reliability is improved, but system cost and memory overhead increase

Engineering Contradiction:
Improvedata access reliabilityVSAvoidexternal memory quantity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple separate memory structures into a single free buffer pool that serves all virtual HBAs. This unified memory approach reduces the total quantity of external memory required while maintaining data access reliability through proper buffer allocation and management mechanisms using hybrid linked lists.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system implements dynamic buffer allocation where memory buffers are allocated to vHBAs when needed and recovered back to the free pool when no longer needed. This recovery mechanism ensures that memory resources are efficiently reused, maintaining reliability while minimizing the total memory quantity required in the system.

Inventive Principle:
Principle #34Discarding and recovering

3Reliability

If message passing mechanisms are used for buffer management between HBA and I/O device, then communication reliability is improved, but latency increases

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidI/O latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the buffer management communication from the message passing protocol and implements it through direct memory access using shared free buffer pools and hybrid linked lists. This extraction eliminates the overhead of message passing while maintaining communication reliability through direct memory-sharing mechanisms between the HBA and I/O device.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The hybrid linked list structure acts as an intermediary mechanism that enables direct buffer management between the HBA and I/O device without requiring message passing. The linked lists provide a shared data structure that both components can access directly, reducing latency while maintaining reliability through structured buffer allocation and deallocation protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If separate buffer pools are allocated for each virtual HBA, then isolation and security are improved, but memory overhead and system cost increase

Engineering Contradiction:
ImprovevHBA isolationVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges separate buffer pools into a single shared free buffer pool that serves multiple virtual HBAs. Virtualization isolation is maintained through logical separation using hybrid linked lists that track buffer allocation per vHBA, while physical memory is efficiently shared. This approach reduces memory overhead while preserving the isolation and security requirements for each vHBA.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9104637B2System and method for managing host bus adaptor (HBA) over infiniband (IB) using a single external memory interface
Publication Date: 2015.08.11 ORACLE INT CORP
  • US9104637B2 patent drawing
  • US9104637B2 patent drawing
  • US9104637B2 patent drawing

AI summary

A system and method can support input/output (I/O) virtualization in a computing environment. The system can comprise a chip, which is associated with a server on a network fabric. Additionally, the chip is associated with an external memory that contains a plurality of packet buffers. Moreover, an on-chip memory maintains a state of one or more packets that contain disk-read data received from a physical host bus adaptor (HBA). Furthermore, the chip operates to en-queue said one or more packets in the plurality of packet buffers on the external memory, read out said one or more packets from the external memory based on the state of said one or more packets, and send said one or more packets to the server.