HBA MMIO Queue Management Reduces PCIe Bus Access Latency
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Solution Overview
Problem
The existing computer systems using Host Bus Adapters (HBAs) with PCIe buses experience performance bottlenecks due to the high number of accesses required for data transmission and reception through the PCIe bus, leading to slower processing speeds compared to internal HBA operations.
Innovation Solution
Implementing a Memory Mapped I/O (MMIO) area that maps the HBA's storage region onto the main storage, allowing the HBA driver to write management information to the MMIO area, reducing the need for direct PCIe bus accesses between the HBA, CPU, and main storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If HBA uses PCIe bus to access main storage for data transmission/reception, then HBA can communicate with I/O device, but access speed through PCIe bus becomes very low compared to internal HBA operations
Solution Approach 1:
The patent introduces a memory-mapped I/O region as an intermediary between the HBA's internal storage and the main storage. This intermediary allows the HBA to manage data transmission queues and control information without repeatedly accessing the main storage through the slow PCIe bus, thereby resolving the contradiction between communication capability and access speed.
2Ease of operation
If HBA driver and HBA-F/W frequently access main storage through PCIe bus for queue management, then data transmission can be controlled, but number of PCIe bus accesses increases causing performance bottleneck
Solution Approach 1:
The patent pre-allocates a memory-mapped I/O region that contains queue management structures. By preparing these structures in advance within the HBA's accessible memory space, the system eliminates the need for frequent PCIe bus accesses during data transmission operations, thereby reducing processing time while maintaining ease of operation.
Solution Approach 2:
The patent creates a copy of the queue management information in the memory-mapped I/O region within the HBA. Instead of repeatedly accessing the original queue structures in main storage through the PCIe bus, the HBA operates with local copies, significantly reducing the number of PCIe bus accesses and associated delays.
3Extent of automation
If HBA-F/W reads and writes queue information from main storage through PCIe bus, then I/O operations can be managed, but access frequency creates bottleneck in data processing
Solution Approach 1:
The memory-mapped I/O region serves as an intermediary buffer that stores queue management information locally within the HBA. This allows HBA-F/W to read and write queue information without repeatedly traversing the slow PCIe bus to the main storage, thereby maintaining automated I/O management while significantly improving data processing speed.
Data Source
AI summary
An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped.