Host Bus Adapter Port Quiescing for Storage Controller Reinitialization
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Solution Overview
Problem
In storage controller systems, existing technologies face challenges in minimizing the impact of logic errors on response times during recovery, particularly when performing resets on host bus adapters connected to Fibre Channel fabrics, as they often require cold resets or initial program loads, which disrupt active host I/O operations.
Innovation Solution
A method involving two quiesce periods is implemented, where the embedded port of a host bus adapter stops processing incoming frames and DMA access during the first period to reset hardware, and reinitializes internal structures during the second period, allowing for normal I/O operations to resume with minimal disruption, using an application programming interface (API) for communication between the driver and the embedded port.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cold reset or initial program load is performed on the host bus adapter, then the logic errors are cleared and the system is reinitialized, but the active host I/O operations are disrupted and response times increase significantly
Solution Approach 1:
The reset process is segmented into two distinct phases: a first quiesce period for hardware reset and a second quiesce period for driver reinitialization. This segmentation allows the system to perform necessary resets while minimizing disruption to I/O operations by separating the disruptive hardware reset from the less disruptive software reinitialization.
Solution Approach 2:
The embedded port performs preliminary actions by quiescing I/O operations before the hardware reset occurs. This preliminary quiescing prevents new I/O commands from being issued during the reset period, and any pending commands are completed or aborted gracefully, thereby avoiding the need for a full cold reset that would disrupt active operations.
Solution Approach 3:
The system changes the operational parameters of the embedded port dynamically. During the first quiesce period, the port stops processing incoming frames and latches hardware input states. During the second quiesce period, the port allows limited DMA activity and synchronizes queue pointers. These parameter changes enable the reset process to proceed while maintaining system functionality.
2Reliability
If hardware resets are performed on buses and logic connected to the embedded port, then the storage controller elements are reinitialized, but I/O operations must be suspended
Solution Approach 1:
The reinitialization process is divided into two quiesce periods with distinct objectives. The first period handles hardware reset while the second period handles driver reinitialization. This segmentation allows the system to maintain partial I/O functionality during the process, specifically allowing DMA activity during the second period while synchronizing queue pointers, thereby reducing the overall impact on productivity.
Solution Approach 2:
The system maintains continuity of useful action by allowing certain I/O operations to continue during the reset process. Specifically, during the second quiesce period, DMA activity is permitted to continue while queue pointers are synchronized. This ensures that data transfer operations can proceed without complete interruption, maintaining productivity while still achieving the necessary reinitialization.
3Reliability
If the embedded port stops processing incoming frames and latches hardware input states, then hardware can be reset safely, but the port cannot accept new I/O commands
Solution Approach 1:
The embedded port performs preliminary actions by quiescing I/O operations and latching hardware input states before the hardware reset occurs. This preliminary quiescing ensures that the hardware is in a known, stable state for resetting. After the reset, the port is reinitialized and can accept new I/O commands again, maintaining ease of operation despite the temporary suspension during reset.
Solution Approach 2:
The latched hardware input states act as an intermediary mechanism that preserves the state of hardware inputs during the reset process. By latching these states before reset and restoring them after reset, the system maintains the ability to accept and process I/O commands seamlessly, even though the port temporarily stops processing during the reset period.
Data Source
AI summary
An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.