Host Bus Adapter Storage Caching for Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern storage devices face latency issues due to the rotational speed of hard disk drives and the need for additional caching solutions that are not fault-resilient and resource-intensive, as existing caching techniques either consume host system resources or rely on volatile memory.
Innovation Solution
An added level of storage caching is implemented within a host bus adapter (HBA), which provides a transparent caching solution that reduces latency by placing cached data closer to the host system, using solid state memory for reliability and efficiency, and is integrated into the I/O interface card to interface with storage arrays without affecting host or storage system software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If caching is implemented in host system memory, then storage access latency is reduced, but host system resources are consumed and fault resilience is compromised
Solution Approach 1:
The patent segments the caching function from the host system by implementing it in a dedicated storage array controller rather than using host system memory. This creates an independent caching subsystem that serves multiple hosts, eliminating the trade-off between resource consumption and fault resilience.
Solution Approach 2:
The patent introduces an intermediary caching layer in the storage array controller that mediates between the host system and the storage devices. This intermediary provides fault-resilient caching using solid state memory without consuming host system resources, as it operates independently within the storage subsystem.
2Productivity
If caching is implemented in storage system controller, then storage access performance is enhanced, but device complexity increases
Solution Approach 1:
The patent implements a universal caching solution in the storage array controller that serves multiple hosts simultaneously. The caching subsystem is designed to be host-agnostic, providing multi-functional capability that enhances performance without proportionally increasing complexity through economies of scale.
Solution Approach 2:
The patent nests the caching functionality within the existing storage array controller architecture, integrating solid state memory and caching logic into the controller's existing structure. This nested approach leverages existing control pathways and interfaces, minimizing the increase in device complexity while achieving performance enhancement.
3Speed
If volatile memory is used for caching, then access speed is improved, but reliability is reduced due to data loss on power removal
Solution Approach 1:
The patent changes the physical state parameter of the caching memory from volatile to non-volatile by using solid state memory. This parameter change maintains the fast access speeds characteristic of solid state technology while providing the data persistence and fault resilience of non-volatile storage, eliminating the trade-off between speed and reliability.
Data Source
AI summary
The present disclosure provides a method for processing a storage operation in a system with an added level of storage caching. The method includes receiving, in a storage cache, a read request from a host processor that identifies requested data and determining whether the requested data is in a cache memory of the storage cache. If the requested data is in the cache memory of the storage cache, the requested data may be obtained from the storage cache and sent to the host processor. If the requested data is not in the cache memory of the storage cache, the read request may be sent to a host bus adapter operatively coupled to a storage system. The storage cache is transparent to the host processor and the host bus adapter.