Heterojunction Back Contact Cell Fabrication via Selective Etching
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Solution Overview
Problem
Existing methods for forming interdigitated emitter and Back Surface Field regions in silicon heterojunction Interdigitated Back Contact photovoltaic cells require multiple process steps and often use metallic masks or additional deposition steps, which are cumbersome and can affect the p-type a-Si:H layer.
Innovation Solution
A method involving the deposition of a patterned p+ a-Si:H layer, followed by a first intrinsic a-Si:H layer and then an n+ a-Si:H layer, with selective etching in a diluted TMAH solution to achieve good electrical isolation between the layers, reducing process steps and maintaining the integrity of the p+ a-Si:H layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metallic mask is used for patterning the n-type a-Si:H layer, then the electrical isolation between n-type and p-type layers is achieved, but the device complexity increases due to mask attachment and cleaning steps
Solution Approach 1:
A thin intrinsic a-Si:H buffer layer is deposited as an intermediary between the patterned n-type a-Si:H layer and the subsequently deposited p-type a-Si:H layer. This buffer layer acts as a mediator that provides electrical isolation and prevents parasitic shunts, eliminating the need for metallic masks while maintaining reliable electrical separation between the interdigitated contacts.
Solution Approach 2:
The metallic mask and its associated attachment, cleaning, and replacement steps are completely removed from the fabrication process. The electrical isolation function previously achieved by the mask is extracted and replaced by the intrinsic a-Si:H buffer layer, which is deposited directly through the patterned structures without requiring physical masking.
2Reliability
If a silicon oxide layer is deposited by low pressure chemical vapor deposition to separate n-type and p-type a-Si:H layers, then electrical isolation is achieved, but the p-type a-Si:H layer may be affected by the deposition process
Solution Approach 1:
The material composition parameter is changed from silicon oxide to intrinsic a-Si:H for the buffer layer. This material substitution allows deposition under conditions that are less harmful to the p-type a-Si:H layer, while still achieving the required electrical isolation function. The intrinsic a-Si:H buffer layer can be deposited without adversely affecting the integrity of the subsequently deposited p-type doped layer.
3Reliability
If multiple process steps are used to achieve electrical isolation, then the isolation quality is improved, but the manufacturing time increases
Solution Approach 1:
The electrical isolation function is merged into a single thin intrinsic a-Si:H buffer layer deposition step, combining multiple isolation mechanisms into one integrated layer. This single layer simultaneously provides electrical isolation, surface passivation, and serves as a diffusion barrier, eliminating the need for multiple separate process steps while maintaining high isolation quality.
Solution Approach 2:
The intrinsic a-Si:H buffer layer is deposited in advance, before the p-type a-Si:H layer is deposited. This preliminary action establishes the electrical isolation barrier beforehand, preventing parasitic shunts from forming during subsequent processing steps, and eliminates the need for later isolation corrections or additional deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides efficient electrical isolation with a high shunt resistance, reducing the number of process steps and minimizing the risk of damaging the p-type layer, resulting in improved device performance with a self-limiting etching process.
Implementation Method 1
The etching step can be done by wet etching in a diluted TMAH (Tetramethylammonium Hydroxide) solution, preferably at ambient temperature
Implementation Method 2
depositing a thin intrinsic buffer layer
Data Source
Figure 1
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AI summary
The present disclosure provides a method for forming on a substrate a patterned n+ a-Si:H layer and a patterned p+ a-Si:H layer, the patterned n+ a-Si:H layer and the patterned p+ a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising: forming a patterned p+ a-Si:H layer on the substrate, the patterned p+ a-Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed; depositing a first intrinsic a-Si:H layer on the substrate; depositing an n+ a-Si:H layer on the first intrinsic a-Si:H layer; providing a patterned masking layer covering the n+ a-Si:H layer at least in the second regions; and selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer, thereby leaving the underlying p+ a-Si:H layer substantially unaffected, wherein selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer comprises performing an etching step in a diluted TMAH solution.