Hybrid Bonding Interconnect Chiplet for Post-Silicon Debugging
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Solution Overview
Problem
The limited number of view ports and signal/nodes in microchips complicates post-silicon testing and debugging, often requiring time-consuming and expensive focused ion beam (FIB) processes to generate probe points.
Innovation Solution
The implementation of a hybrid bonding interconnect (HBI) architecture allows for a higher density of DFx hooks on the die, enabling more nodes to be viewed without routing them to view pins, using test and/or debug chiplets connected via HBI pads with smaller pitch and size, facilitating easier post-silicon testing and debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If traditional view ports and signal routing are used in microchips, then the chip structure remains simple, but the number of viewable nodes is limited and testing becomes difficult
Solution Approach 1:
The chip is divided into multiple segments including functional blocks, HBI pad arrays, and test chiplets. Each segment can be independently tested through the HBI interconnect architecture, allowing comprehensive testing without requiring all nodes to be routed to view pins. This segmentation enables testing of internal nodes that would otherwise be inaccessible.
Solution Approach 2:
Test chiplets serve as intermediary components between the functional blocks and external testing equipment. These chiplets contain HBI pads that couple to HBI pads on the die, providing indirect access to internal nodes for testing purposes. This intermediary approach allows testing of nodes without requiring direct view port connections.
2Difficulty of detecting and measuring
If FIB process is used to generate probe points, then more nodes can be accessed for testing, but the process becomes time consuming and expensive
Solution Approach 1:
HBI pads and test chiplets are integrated into the chip design before silicon fabrication is complete. This preliminary integration of testing infrastructure allows direct electrical access to internal nodes during post-silicon testing, eliminating the need for time-consuming FIB processes to create probe points after the chip is manufactured.
Solution Approach 2:
The chip design includes self-service testing capabilities through integrated HBI pads and test chiplets. These components provide built-in access points for testing internal nodes, allowing the chip to be tested without requiring external modification processes like FIB. The testing infrastructure serves itself by being part of the original design.
3Quantity of substance
If more view ports are added to microchip, then more nodes can be tested directly, but the practical limit of view ports is reached
Solution Approach 1:
The testing architecture moves from a two-dimensional surface approach (view ports on chip surface) to a three-dimensional approach using HBI pads in arrays that can couple to multiple layers and regions. Test chiplets can access nodes through vertical and lateral dimensions via the HBI interconnect architecture, effectively increasing the number of accessible nodes without adding more surface view ports.
Solution Approach 2:
HBI pads serve multiple functions: they provide interconnect between functional blocks, enable testing access to internal nodes, and support both signal routing and testing operations. This multi-functionality allows a single HBI pad structure to replace what would otherwise require separate view ports and routing infrastructure, increasing node accessibility without proportional increases in complexity.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2~3
AI summary
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.