HBM Bandwidth Aggregation Switch via Interface Die
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Solution Overview
Problem
Existing integrated circuit (IC) packaging technologies face challenges in efficiently integrating high bandwidth memory (HBM) with programmable ICs like FPGAs without disrupting the existing architecture, requiring significant changes and requalification, which is complex and costly.
Innovation Solution
The introduction of an interface die compatible with both the programmable IC and HBM, using interposer interconnections to route signals between the dies without altering the programmable IC, allowing HBM to be integrated without changing the existing IC architecture, and using a shared wafer-level substrate separated by a scribe line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If HBM is integrated directly with programmable IC using existing packaging technologies, then bandwidth capability is improved, but device complexity and requalification requirements increase significantly
Solution Approach 1:
The patent introduces an interface die as an intermediary component between the HBM and the programmable IC. This interface die contains buffer logic that translates between the HBM interface protocol and the programmable IC logic interface, eliminating the need for direct complex integration while achieving high bandwidth capability.
Solution Approach 2:
The system is segmented into three separate components: the HBM die, the interface die with buffer logic, and the programmable IC. This segmentation allows each component to be optimized independently and simplifies the overall integration process while maintaining high bandwidth performance.
2Adaptability or versatility
If existing programmable IC architecture is modified to integrate HBM, then HBM capabilities are added, but qualification time and costs increase
Solution Approach 1:
The interface die acts as a mediator that allows HBM capability to be added without modifying the existing programmable IC architecture. The buffer logic on the interface die handles all HBM-specific protocols and interfaces, leaving the programmable IC unchanged and thus avoiding requalification.
Solution Approach 2:
The interface die serves multiple functions: it provides the HBM interface, contains buffer logic for data translation, and interfaces with the programmable IC logic. This multi-functional design allows HBM capability to be added universally without affecting existing programmable IC designs.
3Ease of manufacture
If programmable IC is altered to connect directly with HBM, then integration is achieved, but existing qualified logic circuits are disrupted
Solution Approach 1:
The interface die with buffer logic serves as an intermediary that isolates the programmable IC from HBM-specific interface requirements. This allows existing qualified logic circuits to remain unchanged while still achieving integration with HBM, thus maintaining reliability.
4Adaptability or versatility
If HBM standards change in the future, then newer standards can be adopted, but programmable logic must be requalified
Solution Approach 1:
The interface die with buffer logic acts as an intermediary that handles all HBM standard-specific protocols. When HBM standards change, only the interface die needs to be updated, not the entire programmable system, thus reducing requalification complexity.
Solution Approach 2:
By segmenting the HBM interface functionality into a separate interface die, the system allows independent updates to HBM standard compatibility without affecting the core programmable logic, simplifying future standard transitions.
Data Source
AI summary
Methods and apparatus are described for adding one or more features (e.g., HBM) to a qualified SSI technology programmable IC region by providing an interface (e.g., an HBM buffer region with a switch network) between the added feature device and the programmable IC region. One example IC package generally includes a package substrate; at least one interposer disposed above the package substrate; a programmable IC region disposed above the interposer; at least one fixed feature die disposed above the interposer; and an interface region disposed above the interposer and configured to couple the programmable IC region to the fixed feature die via a first set of interconnection lines routed through the interposer between a first plurality of ports of the interface region and the fixed feature die and a second set of interconnection lines routed between a second plurality of ports of the interface region and the programmable IC region.