HBM Base Die Signal Mapping for Scalable D2D Interconnects
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Solution Overview
Problem
The integration of high-bandwidth memory (HBM) in superchips is constrained by the edge size of system-on-chip compute dies, limiting the number of HBM interfaces and posing scalability and power efficiency challenges, particularly for AI workloads demanding higher memory bandwidth.
Innovation Solution
A modular link layer design with uniform data mapping and fixed-size packet containers is employed, allowing scalable and adaptable integration of HBM chiplets with AI accelerators, using die-to-die interconnects to expand bandwidth and maintain low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If die-to-die interconnects are used to extend the beachfront and link additional HBM chiplets, then the memory bandwidth is improved, but the device complexity and integration challenges increase
Solution Approach 1:
The system is divided into separate chiplets (compute die, HBM dies, I/O die) connected through standardized D2D interconnects. Each chiplet can be independently manufactured and tested, then assembled into a superchip. This segmentation allows multiple HBM chiplets to be linked to the compute die without increasing the complexity of individual components, resolving the contradiction between achieving high bandwidth and managing integration challenges.
Solution Approach 2:
A universal D2D interconnect interface is implemented across all chiplet types (compute, HBM, I/O), allowing the same interconnect technology to serve multiple functions: connecting HBM to compute die, enabling peer-to-peer communication between chiplets, and providing scalable expansion. This multi-functionality reduces integration complexity by using a standardized interface rather than custom connections for each chiplet pair.
2Productivity
If more HBM dies are integrated to increase total bandwidth, then the memory bandwidth is improved, but the area requirements and power consumption increase
Solution Approach 1:
Instead of expanding the beachfront area of a single compute die to accommodate more HBM interfaces, the system uses D2D interconnects to connect HBM chiplets in additional dimensions - through vertical stacking and lateral expansion on the substrate. This allows multiple HBM dies to be integrated without increasing the compute die area, as the expansion occurs in the interconnect network dimension rather than the compute die footprint dimension.
3Productivity
If custom logic is designed for each configuration to achieve optimal performance, then the productivity is improved, but the device complexity and cost increase
Solution Approach 1:
The D2D interconnect implements a universal packet-based interface that can handle different chiplet types, speeds, and configurations through a single standardized protocol. The link layer includes adaptive logic that automatically configures the connection parameters based on the connected chiplets, eliminating the need for custom logic design for each configuration while maintaining optimal performance through automated adaptation.
Data Source
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AI summary
Methods and devices are provided in which a link layer module (506) of a base die in a chiplet receives signals in a memory controller, MC, interface format from MCs (502, 504) of the base die. The signals correspond to memory channels in the chiplet. The link layer module (506) converts the signals into a signal in a die-to-die, D2D, packet format based on a mapping ratio between the MCs (502, 504) and the link layer module (506). The link layer module (506) sends the signal in the D2D packet format to a D2D module of the base die. The chiplet is disposed on an interface or substrate of a superchip.