HBM Cache Manager Logic Die Architecture

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Solution Overview

Problem

Existing systems using High Bandwidth Memory (HBM) as cache memory burden the host and the interface between the host and HBM, necessitating an improved method for cache management.

Innovation Solution

Incorporating a cache manager within the logic die of the HBM stack, which includes an address translator, command translator, and tag comparator, operating in compliance with the JESD235A standard, to manage cache operations and reduce the host's workload.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a cache manager is placed on the host to manage HBM cache operations, then cache management functions can be performed, but the host and interface between host and HBM are burdened

Engineering Contradiction:
Improvecache management operationVSAvoidhost and interface complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The cache manager is extracted from the host system and relocated to the logic die within the HBM stack. This extraction removes the cache management burden from the host and interface, allowing them to focus on their primary functions while the cache manager handles cache-specific operations locally within the HBM architecture

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The cache manager acts as an intermediary component embedded within the HBM logic die, mediating between the HBM memory array and external hosts. It translates and manages cache operations locally, serving as an intelligent interface that reduces the complexity burden on both the host and the physical interface between host and HBM

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If cache operations are executed remotely from the HBM stack, then the host has centralized control, but processing load on the host increases and performance decreases

Engineering Contradiction:
Improvecache operation speedVSAvoidhost processing load
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The cache manager is merged with the logic die within the HBM stack, combining cache management functionality with the memory controller in a single integrated unit. This merging enables cache operations to be executed locally within the HBM stack, improving productivity by reducing access latency and decreasing the processing load on external hosts

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the cache manager is integrated into the logic die of the HBM stack, then cache operations can be executed locally improving performance, but the logic die becomes more complex

Engineering Contradiction:
Improvecache operation efficiencyVSAvoidlogic die complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The cache manager utilizes the third dimension provided by the 3D-stacked HBM architecture, embedding the cache management logic within the logic die that is itself stacked with memory dies. This dimensional integration allows cache operations to be performed locally at the memory stack level, improving efficiency while distributing complexity across the vertical stack rather than concentrating it in a single planar layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10180906B2HBM with in-memory cache manager
Publication Date: 2019.01.15 SAMSUNG ELECTRONICS CO LTD
  • US10180906B2 patent drawing
  • US10180906B2 patent drawing
  • US10180906B2 patent drawing

AI summary

A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.